Scalable tree structured high speed input/output subsystem architecture
First Claim
1. An input/output subsystem for a computer system, the computer system having a means for providing and receiving addresses and data to perform operations, the input/output subsystem comprising:
- a plurality of addressable input/output devices receiving and providing packets, each of said input/output devices having an address range unique to that input/output device, each of said packets having a plurality of fields according to a predetermined protocol, said packets including a command portion and being formed of a plurality of elements; and
means connected to said means for providing and receiving addresses and data and each of said plurality of input/output devices for transferring data between said means for providing and receiving addresses and data and each of said plurality of input/output devices, each of said plurality of input/output devices separately connected to said means for transferring,wherein said means for transferring includes;
means for determining if an address and data operation is or a plurality of address and data operations are directed to one of said plurality of input/output devices by analyzing said address portion of said operation or operations to determine if the address provided in said address portion of said operation or operations corresponds to an address within one of said unique address ranges of said plurality of input/output devices;
means for converting said address and data operation or said plurality of address and data operations to a packet;
means for transmitting said packet developed by said means for converting to a packet to said one of said plurality of input/output devices as a series of said plurality of elements forming said packet;
means for receiving a packet from one of said plurality of input/output devices as a series of said plurality of elements forming said packet;
means for converting said packet received from said one of said plurality of input/output devices to an address and data operation or a plurality of address and data operations; and
means for providing the output of said means for converting said packet to said means for providing and receiving addresses and data.
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Accused Products
Abstract
A point to point connection architecture for a computer I/O subsystem, resulting in a scalable tree structure. A Master I/O Concentrator (MIOC) is connected to the host bus and handles conversion between a bus oriented structure and the tree structure of the I/O subsystem. Ports away from the host bus are downstream ports and conform to a simple byte wide message protocol. Various IOCs and devices can be attached to one of the downstream ports on the MIOC. The MIOC directs transmissions to the appropriate channel based on a geographical addressing scheme. The IOC connections act as further points of branching. Ultimately IOD or I/O devices are reached, having an upstream port for connection to the IOC and a downstream port and internal logic appropriate for the particular peripheral device. Various registers are present in the IOCs and the IODs to allow determination of the topology and particular devices present. Messages and commands are transferred in the I/O subsystem in defined packets. Various read, write and exchange commands are used, with a read response being utilized to allow split transaction read operations. Certain status and control commands are also present. Interrupts are handled by having the interrupt levels correspond to memory addresses of the programmable interrupt controller, thus allowing simple selection of interrupts to be generated by the devices and no need for separate wiring.
49 Citations
27 Claims
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1. An input/output subsystem for a computer system, the computer system having a means for providing and receiving addresses and data to perform operations, the input/output subsystem comprising:
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a plurality of addressable input/output devices receiving and providing packets, each of said input/output devices having an address range unique to that input/output device, each of said packets having a plurality of fields according to a predetermined protocol, said packets including a command portion and being formed of a plurality of elements; and means connected to said means for providing and receiving addresses and data and each of said plurality of input/output devices for transferring data between said means for providing and receiving addresses and data and each of said plurality of input/output devices, each of said plurality of input/output devices separately connected to said means for transferring, wherein said means for transferring includes; means for determining if an address and data operation is or a plurality of address and data operations are directed to one of said plurality of input/output devices by analyzing said address portion of said operation or operations to determine if the address provided in said address portion of said operation or operations corresponds to an address within one of said unique address ranges of said plurality of input/output devices; means for converting said address and data operation or said plurality of address and data operations to a packet; means for transmitting said packet developed by said means for converting to a packet to said one of said plurality of input/output devices as a series of said plurality of elements forming said packet; means for receiving a packet from one of said plurality of input/output devices as a series of said plurality of elements forming said packet; means for converting said packet received from said one of said plurality of input/output devices to an address and data operation or a plurality of address and data operations; and means for providing the output of said means for converting said packet to said means for providing and receiving addresses and data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A computer system comprising:
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a plurality of processors, each processor including a central processing unit performing address and data operations, memory and an input/output system interface means to provide and receive packets to perform operations, each of said packets having a plurality of fields according to a predetermined protocol, said packets including a command portion and being formed of a plurality of elements and being directed to a particular address; and a plurality of addressable input/output devices receiving and providing packets, each of said input/output devices having an address range unique to that input/output device, each of said input/output devices including means separately connected to said input/output system interface means of each of said processors for providing and receiving packets, wherein each of said input/output system interface means includes; means for determining if an address and data operation is or a plurality of address and data operations are directed to one of said plurality of input/output devices by analyzing said addresses provided by said central processing unit to determine if the address provided by said central processing unit corresponds to an address within one of said unique address ranges of said plurality of input/output devices; means for converting said address and data operation or said plurality of address and data operations to a packet; means for transmitting said packet developed by said means for converting to a packet to said one of said plurality of input/output devices as a series of said plurality of elements forming said packet; means for receiving a packet from one of said plurality of input/output devices as a series of said plurality of elements forming said packet; means for converting said packet received from said one of said plurality of input/output devices to an address and data operation or a plurality of address and data operations; and means for providing the output of said means for converting said packet to said input/output interface means of each of said processors. - View Dependent Claims (19, 20)
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21. A computer system comprising:
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a microprocessor performing address and data operations and having a graphics interface means to receive and provide packets and an input/output system interface means to receive and provide packets, each of said packets having a plurality of fields according to a predetermined protocol, said packets including a command portion and being formed of a plurality of elements and being directed to a particular address; a main memory connected to said microprocessor; a graphics controller connected to said graphics interface means; and an input/output system connected to said input/output system interface means, said input/output system including; a plurality of addressable input/output devices receiving and providing packets each of said input/output devices having an address range unique to that input/output device; and means separately connected to said input/output system interface means and each of said plurality of input/output devices for transferring data between said microprocessor and each of said plurality of input/output devices, wherein said means for transferring includes; means for determining if a packet is directed to one of said plurality of input/output devices by analyzing said address portion of said packet to determine if the address provided in said address portion of said packet corresponds to an address within one of said unique address ranges of said plurality of input/output devices; means for transmitting said packet to said one of said plurality of input/output devices as a series of said plurality of elements forming said packet; means for receiving a packet from one of said plurality of input/output devices as a series of said plurality of elements forming said packet; and means for providing said received packet to said input/output system interface means. - View Dependent Claims (22, 23, 24, 25, 26, 27)
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Specification