Real time programmable signal processor architecture

• US 5,590,349 A
• Filed: 06/18/1992
• Issued: 12/31/1996
• Est. Priority Date: 07/11/1988
• Status: Expired due to Term

• Current Assignee: Logic Devices Incorporated
• Original Assignee: Logic Devices Incorporated
• Inventors: Robinson, Jeffrey I., Rouse, Keith, Musicus, Bruce R.
• Primary Examiner(s): Treat, William M.
• Application Number:
  US07/900,536
• Time in Patent Office: 1,657 Days
• Field of Search: 395/800, 395/200.03, 395/200.19, 364/474.24
• US Class Current: 712/36
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 15/7835 on more than one IC chip
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

A programmable integrated signal processor ("SPROC") is provided having a multiported central memory unit (RAM), a program memory, at least one, and preferably a plurality of digital processors coupled to the multiported RAM and to the program memory, a data flow manager which controls external data flowing into the SPROC and processed data flowing out of the SPROC by acting as an interface of such data with the multiported RAM, input and output ports coupled to the DFM and acting as serial interfaces for the SPROC, and a host port permitting the programming of the SPROC and acting as a parallel interface to the SPROC. SPROCs may be coupled via the input and output ports to provide a system. The SPROC architecture permits the SPROC system to be computationally expandable, to have low latency and parasitic overhead for real time I/O, to efficiently execute a multiple of asynchronous processes, and to easily interface with microprocessors of various formats. The SPROC architecture in conjunction with a compiler and user interface system permits a user to "sketch and realize" complex circuits in the SPROC. An access port coupled to the multiported data RAM and the program RAM is provided for debugging purposes and permits reading and writing to data and program RAM memory locations. A probe permits monitoring of a memory location and provides an analog signal indicative thereof. The SPROC accomplishes for signal processing that which a microprocessor accomplishes for logic processing, and is further also easily realized in silicon.

Claims

1. A programmable, real time, signal processor apparatus designed for semiconductor integration, which receives regularly clocked data signals from means external said signal processor apparatus, and processes said data signals in a real time fashion, thereby generating processed data signals which are available external to said processor apparatus as regularly clocked output signals, comprising:

a) at least one data signal receiving means for receiving said regularly clocked data signals from said means external said signal processor apparatus;

b) a multiported central memory unit coupled to said data signal receiving means for storing said received data signals, said data signal receiving means including means for regularly forwarding said received data signals to desired locations in said multiported central memory unit;

c) a plurality of digital processor means coupled to said multiported central memory unit, for obtaining said data signals from said multiported central memory unit, for processing said data signals thereby generating processed data signals, and for sending said processed data signals for storage in said multiported central memory unit;

d) a program memory means coupled to said plurality of digital processors for storing microinstructions for said plurality of digital processors, wherein said digital processors process said data signals according to said microinstructions stored in said program memory means;

e) at least one output port coupled to said multiported central memory unit for obtaining said processed data signals from said multiported central memory unit and providing said processed data signals as regularly clocked output signals to means external to said processor apparatus; and

f) at least one data bus coupling said plurality of digital processor means, said at least one output port, and said at least one data signal receiving means to said multiported central memory unit, wherein substantially all data received by said data receiving means is forwarded via said at least one data bus to said multiported central memory unit, obtained from said multiported central memory unit via said at least one data bus and processed by at least one of said plurality of digital processor means to generate said processed data signals, and said processed data signals are forwarded via said at least one data bus to said multiported cental memory unit for either obtaining via said at least one data bus by at least one of said plurality of digital processor means for additional processing or for obtaining via said at least one data bus and output by said at least one output port as a regularly clocked output signal at a rate related to the rate of said received regularly clocked data signals.

2. A processor apparatus according to claim 1, wherein:

said multiported central memory unit comprises a data RAM, and said at least one data bus comprises a data RAM bus, wherein said plurality of digital processors, said data signal receiving means and said output port are coupled to said data RAM bus, whereby access to said data RAM bus is time division multiplexed.

3. A processor apparatus according to claim 2, further comprising:

g) a program bus coupled to said program memory means, and said plurality of digital processors, whereby access to said program bus by said plurality of digital processors is time division multiplexed.

4. A processor apparatus according to claim 2, further comprising:

g) a logic control port for obtaining at least said microinstructions; and

h) a program bus coupled to said program memory means,

wherein said program memory means is programmed in a boot mode of said processor apparatus by forwarding said microinstructions from means external to said processor apparatus through said logic control port and over said program bus to said program memory means.

5. A processor apparatus according to claim 4, wherein:

said logic control port comprises a host port, said host port being coupled to said program memory means via said program bus and coupled to said data RAM via said data RAM bus.

6. A processor apparatus according to claim 5 in conjunction with a parallel host bus coupled to said host port, wherein said program bus and said data RAM bus are bit parallel buses.

7. A processor apparatus according to claim 5 in conjunction with a programmed ROM, said programmed ROM constituting said means external to said processor apparatus,

wherein said programmed ROM contains said microinstructions for said program memory means and further contains configuration information for said data RAM, said data signal receiving means, and said output port, and parametric data for said data RAM, said microinstructions, configuration information, and parametric data having been compiled into said programmed ROM, and

wherein in a master mode of said processor apparatus said processor apparatus

reads said microinstructions from said programmed ROM via said logic control port and sends said microinstructions to said program memory means for storage therein via said program bus,

reads said configuration information from said programmed ROM via said logic control port and sends said configuration information appropriately to said data RAM, to said data signal receiving means, and to output port via said data RAM bus, and

reads said parametric data from said programmed ROM via said logic control port and sends said parametric data to said data RAM.

8. A processor apparatus according to claim 7, further comprising:

i) a boot ROM, said boot ROM being coupled to one of said plurality of digital processor means when said processor apparatus is a master processor apparatus in boot mode, said boot ROM containing boot microcode for causing said digital processor coupled to said boot ROM to control said logic control port and to obtain said microinstructions, configuration information, and parametric data from said programmed ROM.

9. A processor apparatus according to claim 2, further comprising:

g) a data access port coupled to said data RAM via said RAM bus for writing to and/or reading from, via said RAM bus, at least one location of said data RAM.

10. A processor apparatus according to claim 9, wherein:

said data access port is further coupled to said program memory means, and said data access port writes to and/or reads from at least one location of said program memory means.

11. A processor apparatus according to claim 8, further comprising:

j) a data access port coupled to said data RAM unit via said RAM bus for writing to and/or reading from, via said RAM bus, at least one location of said data RAM.

12. A processor apparatus according to claim 9, wherein:

said data access port is further coupled to said program memory means, and said data access port writes to and/or reads from at least one location of said program memory means.

13. A processor apparatus according to claim 2, further comprising:

g) a probe for monitoring a desired address of said data RAM, for obtaining and converting data at said desired address into an analog signal and for supplying said analog signal to a means external said processor apparatus.

14. A processor apparatus according to claim 13, wherein:

said data RAM bus is comprised of a plurality of data lines and a plurality of address lines, and

said probe comprises,

comparator means coupled to said address lines of said data RAM bus for comparing said desired address of said data RAM which is to be probed with addresses appearing on said address lines of said data RAM bus,

means for writing data appearing on said data lines of said data RAM bus to a predetermined location in said data RAM when said comparator means finds a match between said desired address and one of said addresses appearing on said address lines of said data RAM bus,

means for reading said data written to said predetermined location of said data RAM, and

means for converting said data read from said predetermined location of said data RAM into an analog signal.

15. A processor apparatus according to claim 9, further comprising:

h) a probe for monitoring a desired address of said data RAM, for obtaining and converting data at said desired address into an analog signal and for supplying said analog signal to means external said processor apparatus.

16. A processor apparatus according to claim 15, wherein:

said data RAM bus is comprised of a plurality of data lines and a plurality of address lines, and

said probe comprises,

comparator means coupled to said address lines of said data RAM bus for comparing said desired address of said data RAM which is to be probed with addresses appearing on said address lines of said data RAM bus,

means for writing data appearing on said data lines of said data RAM bus to a predetermined location in said data RAM when said comparator means finds a match between said desired address and one of said addresses appearing on said address lines of said data RAM bus,

means for reading said data written to said predetermined location of said data RAM, and

means for converting said data read from said predetermined location of said data RAM into an analog signal.

17. A processor apparatus according to claim 11, further comprising:

k) a probe for monitoring a desired address of said data RAM, for obtaining and converting data at said desired address into an analog signal and for supplying said analog signal to means external said processor apparatus.

18. A processor apparatus according to claim 17, wherein:

said data RAM bus is comprised of a plurality of data lines and a plurality of address lines, and

said probe comprises,

comparator means coupled to said address lines of said data RAM bus for comparing said desired address of said data RAM which is to be probed with addresses appearing on said address lines of said data RAM bus,

means for writing data appearing on said data lines of said data RAM bus to a predetermined location in said data RAM when said comparator means finds a match between said desired address and one of said addresses appearing on said address lines of said data RAM bus,

means for reading said data written to said predetermined location of said data RAM, and

means for converting said data read from said predetermined location of said data RAM into an analog signal.

19. A processor apparatus according to claim 1, wherein:

said at least one data signal receiving means comprises a plurality of data signal receiving means,

said at least one output port coupled to said multiported central memory unit comprises a plurality of output ports, and

said plurality of data signal receiving means and said plurality of ports each include interface means for making said plurality of data signal receiving means and said plurality of ports compatible with the clocking and bit width of a plurality of different means external said processor apparatus.

20. A processor apparatus according to claim 8, wherein:

said at least one data signal receiving means comprises a plurality of data signal receiving means,

said at least one output port coupled to said multiported central memory unit comprises a plurality of output ports, and

said plurality of data signal receiving means and said plurality of ports each include interface means for making said plurality of data signal receiving means and said plurality of ports compatible with the clocking and bit width of a plurality of different means external said processor apparatus.

21. A processor apparatus according to claim 18, wherein:

said at least one data signal receiving means comprises a plurality of data signal receiving means,

said at least one output port coupled to said multiported central memory unit comprises a plurality of output ports, and

said plurality of data signal receiving means and said plurality of ports each include interface means for making said plurality of data signal receiving means and said plurality of ports compatible with the clocking and bit width said plurality of different means external said processor apparatus.

22. A processor apparatus according to claim 20, wherein:

each of said plurality of data signal receiving means includes means for writing data to respective desired first addresses in said data RAM in a repeated sequential fashion, and

each of said plurality of output ports includes means for obtaining in a repeated sequential fashion said processed data signals from respective second addresses of said data RAM.

23. A processor apparatus according to claim 21, wherein:

each of said plurality of data signal receiving means includes means for writing data to respective desired first addresses in said data RAM in a repeated sequential fashion, and

each of said plurality of output ports includes means for obtaining in a repeated sequential fashion said processed data signals from respective second addresses of said data RAM.

24. A system comprising a plurality of said processor apparatuses of claim 3, wherein a first of said plurality of said processor apparatuses has its output port coupled to the data signal receiving means of at least a second of said plurality of said processor apparatus.

25. A system according to claim 24, wherein one of said processor apparatuses is a master processor apparatus, all other processor apparatuses being slave processor apparatuses, and wherein said master processor apparatus and said slave processor apparatuses all each further comprise

g) a host port for receiving microinstructions for the respective processor apparatus;

and

h) a program bus coupling said host port and said program memory means of respective processor apparatuses,

said host port being coupled to said data RAM via said data RAM bus of the respective processor apparatus,

wherein said program memory means of respective slave processor apparatuses are programmed in a boot mode by forwarding said microinstructions from means external to said slave processor apparatuses through said host port, over said program bus and to said program memory means.

26. A system according to claim 25 in conjunction with a programmed ROM, said programmed ROM constituting said means external to said slave processor apparatuses and coupled to said master processor apparatus in boot mode,

wherein said programmed ROM contains said microinstructions for said program memory means of said master processor apparatus and said slave processor apparatuses and further contains configuration information for said data RAM, said data signal receiving means, and said output port of said master and slave processor apparatuses, and parametric data for said data RAM of said master processor apparatus and said slave processor apparatuses, said microinstructions configuration information, and parametric data having been compiled into said programmed ROM, and

wherein said master processor apparatus reads said microinstructions from said programmed ROM via the host port of said master processor apparatus and sends said microinstructions to respective program memory means of said master and slave processor apparatus for storage therein via respective program memory buses, and said master processor apparatus reads said configuration information from said programmed ROM via said master processor apparatus host port and sends said configuration information appropriately to said data RAM, said data signal receiving means, and said output port, of said respective master and slave processor apparatuses via respective data RAM buses, and said master processor apparatus reads said parametric data from said programmed ROM via said master processor apparatus host port and sends said parametric data to appropriate data RAMs of said respective master and slave processor apparatuses via respective data RAM buses.

27. A system according to claim 26, wherein:

said master processor apparatus further comprises a boot ROM, said boot ROM being coupled to one of said digital processors of said master processor apparatus when said master processor apparatus is in boot mode, said boot ROM containing boot microcode for causing said digital processor to control said host port of said master processor apparatus and to obtain said microinstructions, configuration information, and said parametric data from said programmed ROM.

28. A processor apparatus according to claim 25, wherein:

at least one of said master processor apparatus and said slave processor apparatuses includes a data access port coupled to a respective data RAM via a respective data RAM bus for writing to and/or reading from, via said data RAM bus, at least one location of the respective data RAM.

29. A processor apparatus according to claim 28, wherein:

said data access port is further coupled to a respective program memory means, and said data access port writes to and/or reads from at least one location of said respective program memory means.

30. A processor apparatus according to claim 25, wherein:

at least one of said master processor apparatus and said processor apparatuses includes a probe for monitoring a desired address of the data RAM of the respective processor apparatus of the probe, for obtaining and converting data at said desired address into an analog signal and for supplying said analog signal to a means external said processor apparatus.

31. A processor apparatus according to claim 30, wherein:

said data RAM buses of said master and slave processor apparatuses are comprised of a plurality of data lines and a plurality of address lines, and

said probe comprises,

comparator means coupled to said address lines of said respective data RAM bus for comparing said desired address of said RAM which is to be probed with addresses appearing on said address lines of said data RAM bus,

means for writing data appearing on said data lines of said data RAM bus to a predetermined location in said data RAM when said comparator means finds a match between said desired address and one of said addresses appearing on said address lines of said data RAM bus,

means for reading said data written to said predetermined location of said data RAM, and

means for converting said data read from said predetermined location of said data RAM into an analog signal.

32. A programmable real time signal processor apparatus designed for semiconductor integration, which receives regularly clocked data signals from means external said signal processor apparatus, and processes said regularly clocked data signals thereby generating processed data signals which are available external to said processor apparatus as regularly clocked output signals, comprising:

a) at least one data signal receiving means for receiving said regularly clocked data signals from said means external said signal processor apparatus, each data signal receiving means including means for writing data to a plurality of desired first address locations in a multiported central memory unit in a repeated sequential fashion;

b) said multiported central memory unit coupled to said at least one data signal receiving means, said multiported central memory unit for storing said received data signals;

c) a digital processor means coupled to said multiported central memory unit, for obtaining said data signals from said first addresses of said multiported central memory unit, for processing said data signals and thereby generating processed data signals, and for sending said processed data signals for storage in second address locations of said multiported central memory unit;

d) at least one data output means coupled to said multiported central memory unit, for obtaining in a repeated sequential fashion said processed data signals from said second address locations of said multiported central memory unit at a rate related to the rate of said regularly clocked data signals, and for providing said processed data signals as regularly clocked output signals available external to said processor apparatus,

wherein substantially all signal data received by said processor apparatus flows directly from said at least one said data signal receiving means to said multiported central memory unit and said digital processor means obtains data signals for processing substantially only from said multiported central memory unit and provides said processed data signals substantially only to said multiported central memory unit, and wherein said data signal receiving means and said output means handle data flow into and out of said processor apparatus and permit said digital processor means to function substantially free of data input interrupts.

33. A processor apparatus according to claim 32, wherein:

said multiported central memory unit comprises a data RAM and a data RAM bus, wherein said digital processor means, said data signal receiving means, and said output means are coupled to said data RAM bus, whereby access to said data RAM bus is time division multiplexed.

34. A processor apparatus according to claim 32, wherein:

said multiported central memory unit comprises a data RAM and a data RAM bus, and said digital processor means, said data signal receiving means, and said output means are coupled to said data RAM bus, said processor apparatus further comprising,

e) a program memory means coupled to said digital processor means for storing microinstructions for said digital processor means, wherein said digital processor means processes said data signals according to said microinstructions stored in said program memory.

35. A processor apparatus according to claim 34, further comprising:

f) a program bus coupled to said program memory means, and said digital processor.

36. A processor apparatus according to claim 35, further comprising:

g) a logic control port for obtaining at least said microinstructions;

wherein said program memory means is programmed in a boot mode of said processor apparatus by forwarding said microinstructions from means external to said processor apparatus through said logic control port and over said program bus to said program memory means.

37. A processor apparatus according to claim 36, wherein:

said logic control port comprises a host port, said host port being coupled to said program memory means via said program bus and coupled to said data RAM via said data RAM bus.

38. A processor apparatus according to claim 37 in conjunction with a parallel host bus coupled to said host port, wherein said program bus and said data RAM bus are bit parallel buses.

39. A processor apparatus according to claim 36 in conjunction with a programmed ROM, said programmed ROM constituting said means external to said processor apparatus,

wherein said programmed ROM contains said microinstructions for said program memory means and further contains configuration information for said data RAM, said data signal receiving means, and said output means, and parametric data for said data RAM, said microinstructions, configuration information, and parametric data having been compiled into said programmed ROM, and

wherein in a master mode of said processor apparatus said processor apparatus

reads said microinstructions from said programmed ROM via said host port and sends said microinstructions to said program memory means for storage therein via said program bus,

reads said configuration information from said programmed ROM via said host port and sends said configuration information appropriately to said data RAM, to said data signal receiving means, to send means for writing data, and to said data output means via said data RAM bus, and

reads said parametric data from said programmed ROM via said host port and sends said parametric data to said data RAM.

40. A processor apparatus according to claim 39, further comprising:

h) a boot ROM, said boot ROM being coupled to said digital processor means when said processor apparatus is a master processor apparatus in boot mode, said boot ROM containing boot microcode for causing said digital processor means coupled to said boot ROM to control said logic control port and to obtain said microinstructions, configuration information, and parametric data from said programmed ROM.

41. A processor apparatus according to claim 34, further comprising:

f) a data access port coupled to said data RAM via said RAM bus for writing to and/or reading from, via said RAM bus, at least one location of said data RAM.

42. A processor apparatus according to claim 41, wherein:

said data access port is further coupled to said program memory means, and said data access port writes to and/or reads from at least one location of said program memory means.

43. A processor apparatus according to claim 40, further comprising:

i) a data access port coupled to said data RAM unit via said RAM bus for writing to and/or reading from, via said RAM bus, at least one third location of said data RAM.

44. A processor apparatus according to claim 43, wherein:

said data access port is further coupled to said program memory means, and said data access port writes to and/or reads from at least one location of said program memory means.

45. A processor apparatus according to claim 34, further comprising:

f) a probe for monitoring a desired address of said data RAM, for obtaining and converting data at said desired address into an analog signal and for supplying said analog signal to a means external said processor apparatus.

46. A processor apparatus according to claim 45, wherein:

said data RAM bus is comprised of a plurality of data lines and a plurality of address lines, and

said probe comprises,

comparator means coupled to said address lines of said data RAM bus for comparing said desired address of said data RAM which is to be probed with addresses appearing on said address lines of said data RAM bus,

means for writing data appearing on said data lines of said data RAM bus to a predetermined location in said data RAM when said comparator means finds a match between said desired address and one of said addresses appearing on said address lines of said data RAM bus,

means for reading said data written to said predetermined location of said data RAM, and

means for converting said data read from said predetermined location of said data RAM into an analog signal.

47. A processor apparatus according to claim 41, further comprising:

g) a probe for monitoring a desired address of said data RAM, for obtaining and converting data at said desired address into an analog signal and for supplying said analog signal to means external said processor apparatus.

48. A processor apparatus according to claim 47, wherein:

said data RAM bus is comprised of a plurality of data lines and a plurality of address lines, and

said probe comprises,

comparator means coupled to said address lines of said data RAM bus for comparing said desired address of said data RAM which is to be probed with addresses appearing on said address lines of said data RAM bus,

means for writing data appearing on said data lines of said data RAM bus to a predetermined location in said data RAM when said comparator means finds a match between said desired address and one of said addresses appearing on said address lines of said data RAM bus,

means for reading said data written to said predetermined location of said data RAM, and

means for converting said data read from said predetermined location of said data RAM into an analog signal.

49. A processor apparatus according to claim 43, further comprising:

j) a probe for monitoring a desired address of said data RAM, for obtaining and converting data at said desired address into an analog signal and for supplying said analog signal to means external said processor apparatus.

50. A processor apparatus according to claim 49, wherein:

said data RAM bus is comprised of a plurality of data lines and a plurality of address lines, and

said probe comprises,

comparator means coupled to said address lines of said data RAM bus for comparing said desired address of said data RAM which is to be probed with addresses appearing on said address lines of said data RAM bus,

means for writing data appearing on said data lines of said data RAM bus to a predetermined location in said data RAM when said comparator means finds a match between said desired address and one of said addresses appearing on said address lines of said data RAM bus,

means for reading said data written to said predetermined location of said data RAM, and

means for converting said data read from said predetermined location of said data RAM into an analog signal.

51. A processor apparatus according to claim 32, wherein:

said at least one data signal receiving means comprises a plurality of data signal receiving means,

said at least one output means coupled to said multiported central memory unit comprises a plurality of output means, each obtaining in a repeated sequential fashion said processed data signals from respective different second address locations of said multiported central memory unit, and for making said processed data signals available external to said processor apparatus, and

said plurality of data signal receiving means and said plurality of output means each include interface means for making said plurality of data signal receiving means and said plurality of output ports compatible with the clocking and bit width of a plurality of different means external said processor apparatus.

52. A processor apparatus according to claim 40, wherein:

said at least one data signal receiving means comprises a plurality of data signal receiving means,

said at least one output means coupled to said multiported central memory unit comprises a plurality of output means, each obtaining in a repeated sequential fashion said processed data signals from respective different second address locations of said multiported central memory unit, and for making said processed data signals available external to said processor apparatus, and

said plurality of data signal receiving means and said plurality of output means each include interface means for making said plurality of data signal receiving means and said plurality of output ports compatible with the clocking and bit width of a plurality of different means external said processor apparatus.

53. A processor apparatus according to claim 50, wherein:

said at least one data signal receiving means comprises a plurality of data signal receiving means,

said at least one output means coupled to said multiported central memory unit comprises a plurality of output means, each obtaining in a repeated sequential fashion said processed data signals from respective different second address locations of said multiported central memory unit, and for making said processed data signals available external to said processor apparatus, and

said plurality of data signal receiving means and said plurality of output means each include interface means for making said plurality of data signal receiving means and said plurality of output ports compatible with the clocking and bit width of a plurality of different means external said processor apparatus.

54. A system comprising a plurality of said processor apparatuses of claim 37, wherein a first of said plurality of said processor apparatuses has its output means coupled to the data signal receiving means of at least a second of said plurality of said processor apparatus.

55. A system according to claim 54, wherein one of said processor apparatuses is a master processor apparatus, all other processor apparatuses being slave processor apparatuses, and wherein said master processor apparatus and said slave processor apparatuses all each further comprise

f) a host port for receiving microinstructions for the respective processor apparatus;

and

g) a program bus coupling said host port and said program memory means of respective processor apparatuses,

said host port being coupled to said data RAM via said data RAM bus of the respective processor apparatus,

wherein said program memory means of respective slave processor apparatuses are programmed in a boot mode by forwarding said microinstructions from means external to said slave processor apparatuses through said host port, over said program bus and to said program memory means.

56. A system according to claim 55 in conjunction with a programmed ROM, said programmed ROM constituting said means external to said slave processor apparatuses and coupled to said master processor apparatus in boot mode,

wherein said programmed ROM contains said microinstructions for said program memory means of said master processor apparatus and said slave processor apparatuses and further contains configuration information for said data RAM, said data signal receiving means, and said output means of said master and slave processor apparatuses, and parametric data for said data RAM of said master processor apparatus and said slave processor apparatuses, said microinstructions configuration information, and parametric data having been compiled into said programmed ROM, and

wherein said master processor apparatus reads said microinstructions from said programmed ROM via the host port of said master processor apparatus and sends said microinstructions to respective program memory means of said master and slave processor apparatus for storage therein via respective program memory buses, and said master processor apparatus reads said configuration information from said programmed ROM via said master processor apparatus host port and sends said configuration information appropriately to said data RAM, said data signal receiving means, said means for writing data, and said output means of said respective master and slave processor apparatuses via respective data RAM buses, and said master processor apparatus reads said parametric data from said programmed ROM via said master processor apparatus host port and sends said parametric data to appropriate data RAMs of said respective master and slave processor apparatuses via respective data RAM buses.

57. A system according to claim 56, wherein:

said master processor apparatus further comprises a boot ROM, said boot ROM being coupled to said digital processor means of said master processor apparatus when said master processor apparatus is in boot mode, said boot ROM containing boot microcode for causing said digital processor means to control said host port of said master processor apparatus and to obtain said microinstructions, configuration information, and said parametric data from said programmed ROM.

58. A processor apparatus according to claim 55, wherein:

at least one of said master processor apparatus and said slave processor apparatuses includes a data access port coupled to a respective data RAM via a respective data RAM bus for writing to and/or reading from, via said data RAM bus, at least one location of the respective data RAM.

59. A processor apparatus according to claim 58, wherein:

said data access port is further coupled to a respective program memory means, and said data access port writes to and/or reads from at least one location of said respective program memory means.

60. A processor apparatus according to claim 55, wherein:

at least one of said master processor apparatus and said processor apparatuses includes a probe for monitoring a desired address of the data RAM of the respective processor apparatus of the probe, for obtaining and converting data at said desired address into an analog signal and for supplying said analog signal to a means external said processor apparatus.

61. A processor apparatus according to claim 60, wherein:

said data RAM buses of said master and slave processor apparatuses are comprised of a plurality of data lines and a plurality of address lines, and

said probe comprises,

comparator means coupled to said address lines of said respective data RAM bus for comparing said desired address of said RAM which is to be probed with addresses appearing on said address lines of said data RAM bus,

means for writing data appearing on said data lines of said data RAM bus to a predetermined location in said data RAM when said comparator means finds a match between said desired address and one of said addresses appearing on said address lines of said data RAM bus,

means for reading said data written to said predetermined location of said data RAM, and

means for converting said data read from said predetermined location of said data RAM into an analog signal.

62. A system for implementing in substantially integrated circuit format different circuits defined by textual or graphical high level description, comprising:

a) a development system having

1) memory means storing a cell library, said cell library including a plurality of functional block elements useful in implementing said different circuits, each functional block defined by a set of instructions,

2) circuit definition entry means for choosing said functional block elements of said cell library and for defining interconnections between said functional block elements, said circuit definition entry means including means for entering parameters for a plurality of functional block elements chosen as part of a desired circuit,

3) processor means for compiling said set of instructions and said parameters according to a desired algorithm to create microcode for at least one signal processor apparatus whereby said at least one signal processor apparatus can thereby implement said desired circuit;

b) said signal processor apparatus, for receiving regularly clocked data signals generated external to said signal processor apparatus, for processing said data signals according to said microcode thereby generating processed data signals, and for making said processed data signals available as regularly clocked output signals having a data rate related to the data rate of said regularly clocked data signals to means external to said processor apparatus, said signal processor apparatus including

1) port means for receiving said regularly clocked data signals and for receiving said microcode from said development system,

2) a program memory including a program bus, said program memory coupled to said port means for receiving and storing said microcode,

3) a multiported central memory unit including a data bus, said multiported central memory unit coupled to said port means, said port means including means for forwarding said received data signals to desired locations in said multiported central memory unit, and said multiported central memory unit for storing said received data signals;

4) a digital processor means coupled to said multiported central memory unit and to said program memory, for obtaining said data signals from said multiported central memory unit, for processing said data signals according to said microcode stored in said program memory, and thereby generating processed data signals, and for sending said processed data signals for storage in said multiported central memory unit, and

5) an output means coupled to said multiported central memory unit, for obtaining said processed data signals from said multiported central memory unit, and for making said processed data signals available to said means external said processor apparatus as regularly clocked output signals having a data rate related to the data rate of said regularly clocked data signals.

63. A system according to claim 62, wherein:

said port means comprises a control port and a data signal receiving means, said control port coupled to said development system for receiving said microcode from said development system, and said data signal receiving means for receiving said data signals, said data signal receiving means including said means for forwarding.

64. A system according to claim 63, wherein:

said processor means for compiling further creates configuration information for configuring said data signal receiving means, said multiported central memory unit, and said output means, and parametric data for said multiported central memory unit.

65. A system according to claim 64, wherein:

said signal processor apparatus further comprises

7) a boot ROM, said boot ROM being coupled to said digital processor means when said processor apparatus is a master processor apparatus in boot mode, said boot ROM containing boot microcode for causing said digital processor coupled to said boot ROM to control said control port and to obtain said microinstructions, configuration information, and parametric data from said programmed ROM, and to forward said parametric data to said multiported central memory unit, said microinstructions to said program memory and said configuration information to said data signal receiving means, said multiported central memory unit, and said output means.

66. A system according to claim 65, wherein:

said signal processor apparatus further comprises

8) a data access port coupled to said multiported central memory unit via said data bus for writing to and/or reading from, via said data bus, at least one location of said multiported central memory unit.

67. A system according to claim 66, wherein:

said data access port is further coupled to said program memory, and said data access port writes to and/or reads from at least one location of said program memory.

68. A system according to claim 65, wherein:

said signal processor apparatus further comprises

8) a probe for monitoring a desired address of said multiported central memory unit, for obtaining and converting data at said desired address into an analog signal and for supplying said analog signal to means external said signal processor apparatus.

69. A system according to claim 64, further comprising:

c) a programmed ROM, said programmed ROM for receiving and holding said microinstructions for said program memory means, said configuration information for said multiported central memory unit, said data signal receiving means, and said output means, and parametric data for said data multiported central memory unit, said microinstructions, configuration information, and parametric data having been compiled into said programmed ROM by said processor means for compiling, and

wherein in a master mode of said signal processor apparatus said signal processor apparatus

reads said microinstructions from said programmed ROM via said control port and sends said microinstructions to said program memory means for storage therein via said program bus,

reads said configuration information from said programmed ROM via said control port and sends said configuration information appropriately to said data multiported central memory unit, to said data signal receiving means, and to said output means via said data RAM bus, and

reads said parametric data from said programmed ROM via said host port and sends said parametric data to said data RAM.

70. A system according to claim 65, further comprising:

c) a programmed ROM, said programmed ROM for receiving and holding said microinstructions for said program memory means, said configuration information for said multiported central memory unit, said data signal receiving means, and said output means, and parametric data for said data multiported central memory unit, said microinstructions, configuration information, and parametric data having been compiled into said programmed ROM by said processor means for compiling, and

wherein in a master mode of said signal processor apparatus said signal processor apparatus

reads said microinstructions from said programmed ROM via said control port and sends said microinstructions to said program memory means for storage therein via said program bus,

reads said configuration information from said programmed ROM via said control port and sends said configuration information appropriately to said data multiported central memory unit, to said data signal receiving means, and to said output means via said data RAM bus, and

reads said parametric data from said programmed ROM via said host port and sends said parametric data to said data RAM.

71. A system according to claim 64, wherein:

said at least one data signal receiving means comprises a plurality of data signal receiving means,

said at least one output means coupled to said multiported central memory unit comprises a plurality of output ports, and

said plurality of data signal receiving means and said plurality of ports each include interface means for making said plurality of data signal receiving means and said plurality of ports compatible with the clocking and bit width of a plurality of different means external said processor apparatus.

72. A system according to claim 71, wherein:

each of said plurality of data signal receiving means includes means for writing data to respective desired first addresses in said multiported central memory unit in a repeated sequential fashion, and

each of said plurality of output ports includes means for obtaining in a repeated sequential fashion said processed data signals from respective second addresses of said multiported central memory unit.

73. A system according to claim 64, wherein:

said system includes a plurality of said signal processor apparatuses with the output means of a first of said plurality of said processor apparatuses being coupled to the data signal receiving means of at least a second of said plurality of said processor apparatuses, and wherein one of said processor apparatuses is a master processor apparatus, all other processor apparatuses are slave processor apparatuses.

74. A system according to claim 68, wherein:

said system includes a plurality of said signal processor apparatuses with the output means of a first of said plurality of said processor apparatuses being coupled to the signal data receiving means of at least a second of said plurality of said processor apparatuses, and wherein one of said processor apparatuses is a master processor apparatus, all other processor apparatuses are slave processor apparatuses, and

said programmed ROM further holds microinstructions, configuration informatation, and parametric data for said slave processor apparatuses.

75. A system according to claim 74, wherein:

said at least one data signal receiving means comprises a plurality of data signal receiving means,

said at least one output means coupled to said multiported central memory unit comprises a plurality of output ports, and

said plurality of data signal receiving means and said plurality of ports each include interface means for making said plurality of data signal receiving means and said plurality of ports compatible with the clocking and bit width of a plurality of different means external said processor apparatus.

76. A processor apparatus according to claim 75, wherein:

each of said plurality of data signal receiving means includes means for writing data to respective desired first addresses in said multiported central memory unit in a repeated sequential fashion, and

each of said plurality of output ports includes means for obtaining in a repeated sequential fashion said processed data signals from respective second addresses of said multiported central memory unit.

77. A method for processing information in a real time signal processor apparatus designed for semiconductor integration, said processor apparatus having a data signal receiving means for receiving regularly clocked data signals from a means external to said processor apparatus, a multiported central memory unit coupled to said data signal receiving means, a digital processor means coupled to said multiported central memory unit, and at least one output port coupled to said multiported central memory unit, said method comprising for an operating mode of said processor apparatus:

a) receiving said regularly clocked data signals at said data signal receiving means;

b) forwarding said received data signals in a repeated sequential fashion to a plurality of desired first locations in said multiported central memory unit;

c) causing said digital processor means to obtain said data signals from said multiported central memory unit;

d) processing said data signals in said digital signal processor to generate processed data signals;

e) sending said processed data signals from said digital processor means to said multiported central memory unit for storage in desired second locations in said multiported central memory unit;

f) causing said output port to obtain said processed data signals from said desired second locations in a repeated sequential fashion and to make said processed data signals available to means external to said processor apparatus as regularly clocked output signals having a data rate related to said regularly clocked data signals,

wherein substantially all signal data received by said processor apparatus flow directly from said at least one said data signal receiving means to said multiported central memory unit and said digital processor means obtains data signals for processing substantially only from said multiported central memory unit and provides said processed data signals substantially only to said multiported central memory unit.

78. A method according to claim 77, wherein:

said multiported central memory unit comprises a data RAM and a data RAM bus, and said steps b), c), e), and f) are accomplished in a time division multiplexed manner using said data RAM bus.

79. A method according to claim 77, wherein:

said multiported central memory unit comprises a data RAM and a data RAM bus,

said processor apparatus further comprises a program memory means and a program bus, said program memory means coupled to said digital processor, said program memory means for storing microinstructions for controlling said digital processor, and

said digital processor processes said data signals in said processing step according to said microinstructions stored in said program memory.

80. A method according to claim 77, wherein:

said processor apparatus comprises a plurality of data signal receiving means, and a plurality of output ports, and said steps a)-f) set up a plurality of data paths through said processor apparatus.

81. A method according to claim 78, wherein:

said multiported central memory unit comprises a data RAM and a data RAM bus,

said processor apparatus further comprises a program memory means and a program bus, a plurality of data signal receiving means, and a plurality of output ports, said program memory means coupled to said digital processor for storing microinstructions for said digital processor, and

said digital processor processes said data signals in said processing step according to said microinstructions stored in said program memory, and

steps a)-f) set up a plurality of data paths through said processor apparatus, utilizing said plurality of output ports and said plurality of data signal receiving means.

82. A method according to claim 79, wherein:

said processor apparatus further comprises a logic control port, said logic control port being coupled to a program memory means for storing said microinstructions, said method further comprising for a boot-up mode of said processor apparatus,

reading, via said logic control port during boot-up mode, said microinstructions from an external programmed memory; and

forwarding said microinstructions for storage in said program memory means of said processor apparatus.

83. A method according to claim 82, wherein:

the programmed memory external said processor apparatus further stores configuration information for said data RAM, said data signal receiving means, and said output port, and parametric data for said data RAM, said microinstructions, configuration information, and parametric data having been compiled into the programmed memory external said processor apparatus, said method further comprising for a boot-up mode of said processor apparatus where said processor apparatus is a master processor apparatus,

reading said configuration information from the external programmed memory means via said logic control port,

sending said configuration information appropriately to said data RAM, to said data signal receiving means, and to said output means via said data RAM bus, and

reading said parametric data from the external programmed memory via said logic control port, and

sending said parametric data to said data RAM via said data RAM bus.

84. A method according to claim 83, wherein:

said master processor apparatus further comprises a boot ROM coupled to said digital processor means in a boot mode, said boot ROM containing boot mode microinstructions for causing said digital processor means to control said logic control port so as to obtain said microinstructions, configuration information, and said parametric data from the external programmed memory.

85. A method according to claim 77, wherein:

said multiported central memory unit comprises a data RAM and a data RAM bus, and said processor apparatus further comprises a data access port coupled to said data RAM bus, said method further comprising,

reading via said data access port either data signals or processed data signals from a desired location in said data RAM, and

writing via said data access port replacement data signals for said data signals or processed data signals.

86. A method according to claim 77, wherein:

said multiported central memory unit comprises a data RAM and a data RAM bus having data and address lines, and said processor apparatus further comprises a probe port having address comparator means coupled to said address lines of said data RAM bus, said method further comprising,

monitoring a desired address to be probed of said data RAM by comparing information appearing on said address lines of said data RAM bus with information representing said desired address,

writing data appearing on said data lines of said data RAM bus to a predetermined location in said data RAM when said address comparator means finds a match between said desired address and one of said addresses appearing on said address lines of said data RAM bus,

reading said data written to said predetermined location of said data RAM,

converting said data read from said predetermined location of said data RAM into an analog signal.

87. A method according to claim 79 utilizing a plurality of said processor apparatuses, wherein one of said processor apparatuses is a master processor apparatus, all other processor apparatuses being slave processor apparatuses, and a first of said processor apparatuses has an output port coupled to a data signal input port of a second of said processor apparatuses, said master and slave processor apparatuses each including a logic control port coupled to an external programmed memory, and said master processor apparatus including a boot ROM coupled to said digital processor means in a boot mode, said boot ROM containing boot mode microinstructions for causing said digital processor means to control said logic control port of said master processor apparatus, said method further comprising in a boot-up mode of said processor apparatuses:

reading, via said logic control port of said master processor apparatus said microinstructions, configuration information, and parametric data from an external programmed memory;

sending appropriate of said microinstructions to said program memory means of said master processor apparatus, and other appropriate microinstructions to the program memory means of respective slave processor apparatuses via respective logic control ports;

sending said configuration information appropriately to respective of said data RAMs, said data signal receiving means, and said output means of said master and slave processor apparatuses via respective of said data RAM buses, and

sending said parametric data appropriately to respective of said data RAMs of said master and slave processor apparatuses via respective of said data RAM buses.