Vector processor adopting a memory skewing scheme for preventing degradation of access performance

• US 5,590,353 A
• Filed: 07/15/1994
• Issued: 12/31/1996
• Est. Priority Date: 07/15/1993
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kitai, Katsuyoshi, Sakakibara, Tadayuki, Tanaka, Teruo, Tamaki, Yoshiko, Inagami, Yasuhiro
• Primary Examiner(s): Geckil, Mehmet B.
• Application Number:
  US08/275,388
• Time in Patent Office: 900 Days
• Field of Search: 395/800, 395/728, 395/732, 395/459, 364/736
• US Class Current: 712/4
• CPC Class Codes: G06F 15/8061 Details on data memory access
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3455 using stride
• CPC Class Codes: G06F 9/3824 Operand accessing

Abstract

A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the address decoding is selectively enabled by a selector. The address decoding unit equalizes the periodicities at which the address assignments to the memory modules are skewed or shifted for all the element parallelism factors of the processors belonging to the same machine series. Access request queue is provided in a necessary number of stages in precedence to an access request priority determining unit incorporated in the storage control apparatus.

Claims

1. A vector processor, comprising:

a storage unit including a number (N) of memory modules, which number is given by a power of two and in which an interleave method of successively assigning continuous addresses to memory modules which differ from one to another is adopted;

a number (N) of access request circuits for issuing a number (N) of access requests in parallel for vector data stored in said storage unit; and

a storage control apparatus for transferring the access requests issued by said access request circuits to desired memory modules;

wherein said storage control apparatus includes access request buffer units provided in one-to-one correspondence to said access request circuits holding the access requests, respectively, and an access request priority determining circuit for arbitrating access conflict taking place upon transferring of the access requests from said plurality of access request circuit to said plurality of memory modules;

said storage control apparatus further including address decoder means for determining identification numbers of the transfer destination memory modules from addresses accompanying said access requests issued from said access request circuits, said address decoder means determining identification numbers of said memory modules which differ sequentially in accordance with a predetermined relation formula so long as said addresses vary with a predetermined skew periodicity (m), and which are shifted by a given number every time said address varies by said predetermined skew periodicity (m), said storage control apparatus further including means for making said predetermined skew periodicity (m) equal to skew periodicities of other vector processors which belong to a same system series (same machine or product series) of vector processors and which differ from one another mutually in respect to said number N.

2. A vector processor according to claim 1,

wherein said predetermined periodicity (m) is a value proportional to a maximum value of the values (N) which any one of vector processors belonging to said vector processor system series takes on.

3. A vector processor according to claim 2,

wherein said predetermined periodicity (m) is equal to said maximum value.

4. A vector processor according to claim 2,

wherein said predetermined periodicity (m) is twice as large as said maximum value.

5. A storage control apparatus set forth in claim 1,

further including an access request queue for holding access requests and disposed in precedence to said access request priority determining circuit, wherein said access request queue has a maximum stage number which does not exceed a value given by "m÷

N-m÷

(N×

N).

6. A second vector processor in a system series including a plurality of vector processors having at least a first vector processor and said second vector processor, wherein said first vector processor includes:

a storage unit including a number (N1) of memory modules in which an interleave method of successively assigning continuous addresses to memory modules which differ from one to another is adopted;

a plurality of access request circuits for issuing a plurality of access requests in parallel for vector data stored in said storage unit; and

a storage control apparatus for determining identification numbers of said memory modules from addresses contained in the access requests issued by said access request circuits such that the identification numbers of said memory modules are shifted by a given number every time said address is incremented by a predetermined number of memory modules (m1),

said second vector processor comprising;

a storage unit including a number (N2, where N2≠

N1) of memory modules in which an interleave method of successively assigning continuous addresses to memory modules which differ from one to another is adopted;

a plurality of access request circuits for issuing a plurality of access requests in parallel for vector data stored in said storage unit; and

a storage control apparatus for determining identification numbers of said memory modules from addresses contained in the access requests issued by said access request circuits such that the identification numbers of said memory modules are shifted by a given number every time address is incremented by a predetermined number of memory modules (m2),

wherein the value m1 is used as the value m2.

7. The second vector processor according to claim 6, wherein the value of N1 is larger than the value of N2.

8. The second processor according to claim 7, wherein the value of N1 is the largest in the plurality of vector processors belonging to said system series.

9. The second vector processor according to claim 8, wherein the value of N1 is used as the value of m2.

10. The second vector processor according to claim 8, wherein a value twice that of the value N1 is used as the value m2.

11. A second vector processor in a system series including a plurality of vector processors having at least a first vector processor and said second vector processor, wherein said first vector processor includes:

a storage unit including a number (N1) of memory modules in which an interleave method of successively assigning continuous addresses to memory modules which differ from one to another is adopted;

a number (N1) of access request circuits for issuing a number (N1) of access requests in parallel for vector data stored in said storage unit; and

a storage control apparatus for determining identification numbers of said memory modules from addresses contained in the access requests issued by said access request circuits such that the identification numbers of said memory modules are shifted by a given number every time address is incremented by a predetermined number of memory modules (m1),

said second vector processor includes;

a storage unit including a number (N2, where N2≠

N1) of memory modules in which an interleave method of successively assigning continuous addresses to memory modules which differ from one to another is adopted;

a number (N2) of access request circuits for issuing a number (N2) of access requests in parallel for vector data stored in said storage unit; and

a storage control apparatus for determining identification numbers of said memory modules from addresses contained in the access requests issued by said access request circuits such that the identification numbers of said memory modules are shifted by a given number every time address is incremented by a predetermined number of memory modules (m2),

wherein the value ml is used as the value m2.

12. The second vector processor according to claim 11, wherein the value of N1 is larger than the value of N2.

13. The second processor according to claim 12, wherein the value of N1 is the largest in the plurality of vector processors belonging to said system series.

14. The second vector processor according to claim 13, wherein the value of N1 is used as the value of m2.

15. The second vector processor according to claim 13, wherein a value twice that of N1 is used as the value m2.

16. A vector processor, comprising:

a storage unit including a number (N) of memory modules in which an interleave method of successively assigning continuous addresses to memory modules which differ from one to another is adopted;

a plurality of access request circuits for issuing a plurality of access requests in parallel for vector data stored in said storage unit; and

a storage control circuit including address decoder unit for determining identification numbers of the memory modules from addresses contained in access requests issued from said access request circuits, said addresses being created under element parallelism factor N1, wherein the identification numbers of said memory modules are determined such that the identification numbers of said memory modules are shifted by a given number from a value of N1 every time address is incremented by a predetermined number (m1) of memory modules, and

wherein even when the identification numbers of the memory modules are to be determined from addresses created under element parallelism factor N2, said address decoder unit determines the identification numbers of the memory modules such that the identification numbers of said memory modules are shifted by a given number from the value N1 every time address is incremented by the predetermined number (m1) of memory modules.

17. The vector processor according to claim 16, wherein said address decoder unit comprises:

a first means for determining the identification numbers of the memory modules from addresses contained in said access requests, said addresses being created under element parallelism factor N1; and

a second means for determining the identification numbers of the memory modules from addresses contained in said access requests, said addresses being created under element parallelism factor N2; and

a selection means for switching between said first means and said second means.