Automatic control of distributed DMAs in a PCI bus system supporting dual ISA buses

• US 5,590,377 A
• Filed: 06/07/1995
• Issued: 12/31/1996
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: AST Research, Inc. (Samsung Electronics Co. Ltd.)
• Inventors: Smith, Michael G.
• Primary Examiner(s): Asta, Frank J.
• Application Number:
  US08/481,121
• Time in Patent Office: 573 Days
• Field of Search: 395/427, 395/842, 395/848, 395/200.07, 395/200.08, 364/242.33
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A distributed direct memory access (DMA) system includes specially configured hardware connections between at least one slave DMA controller and a central, or master, DMA controller. The specially configured hardware connections allow the slave DMA controllers to request channel configuration information from the central DMA controller when peripheral devices under the control of the slave DMA controllers make a DMA request. After the channel information is transferred from the master DMA controller to the slave DMA controller, the slave DMA controller is able to process DMA requests for the peripheral devices under its control. In one particular embodiment, the master DMA controller is located in a notebook computer and the slave DMA controller is located in a docking station. The master DMA controller and slave DMA controller communicate when the notebook computer is engaged with the docking station.

Claims

1. A microprocessor-based computer system which provides distributed direct memory access (DMA) for a plurality of peripheral units, said computer system comprising:

a memory;

a central DMA controller in communication with said memory via a system bus, said central DMA controller including registers which store data defining a communication channel associated with one of said peripheral units;

a slave DMA controller in communication with said memory and said central DMA controller via said system bus, said slave DMA controller including registers for storing data defining said communication channel;

a plurality of said peripheral units configured to access said memory, some of said peripheral units in communication with said memory via said central DMA controller and others of said peripheral units in communication with said memory via said slave DMA controller, said peripheral units further configured to include an assigned communication channel; and

a hardware connection between said slave DMA controller and said central DMA controller which allows said slave DMA controller to request channel information in said registers within said central DMA controller when one of said peripheral units in communication with said memory via said slave DMA controller initiates a memory access.

2. A computer system as defined in claim 1, wherein said slave DMA controller includes a state machine which initiates said request of channel information, and wherein said central DMA controller includes a state machine which receives said request of channel information and initiates transfer of said channel information to said slave DMA controller.

3. A method of automatically controlling distributed direct memory accesses (DMAs) in a distributed DMA computer system including a memory, a central DMA controller, a slave DMA controller, and a plurality of peripheral units, said peripheral units having hardware configured channel data defining communication channels associated with each of said peripheral units, said method including the steps of:

configuring said central DMA controller to control direct memory accesses initiated by said peripheral units by storing information in said central DMA controller corresponding to said hardware configured channel data within said peripheral units;

initiating a DMA request from one of said peripheral units to said slave controller;

requesting, from said central DMA controller, channel data corresponding to a communication channel associated with said one of said peripheral units; and

transferring said channel data corresponding to said communication channel associated with said one of said peripheral units from said central DMA controller to said slave DMA controller.

5. A method as defined in claim 3, further comprising the step of acknowledging said DMA request and controlling memory transfer between said requesting peripheral unit and said memory.

4. A method of automatically controlling distributed direct memory accesses (DMAs) in a distributed DMA computer system including a memory, a central DMA controller, a slave DMA controller, and a plurality of peripheral units, said peripheral units having hardware configured channel data defining communication channels associated with each of said peripheral units, said method including the steps of:

configuring said central DMA controller to control direct memory accesses initiated by said peripheral units by storing information in said central DMA controller corresponding to said hardware configured channel data within said peripheral units;

initiating a DMA request from one of said peripheral units to said slave controller;

requesting, from said central DMA controller, channel data corresponding to a communication channel associated with said one of said peripheral units;

transferring said channel data corresponding to said communication channel associated with said one of said peripheral units from said central DMA controller to said slave DMA controller; and

masking said channel data corresponding to said communication channel so that said central DMA controller is no longer enabled to control DMA accesses initiated by said peripheral unit associated with said communication channel.

6. A computer system for automatically controlling direct memory accesses (DMAs) comprising:

a microprocessor;

a memory under the control of said microprocessor;

a system bus;

a central DMA controller in communication with said memory via said system bus, said central DMA controller storing configuration information which provides for control of direct accesses to said memory for selected devices in communication with said system bus;

a slave DMA controller in communication with said system bus, said slave DMA controller also in communication with said central DMA controller via another hardware connection, and wherein said hardware connection provides data to said central DMA controller which designates selected portions of said configuration information which are to be transferred to said slave DMA controller; and

a peripheral unit in communication with said memory via said slave DMA controller and said system bus.

7. A computer system for automatically controlling direct memory accesses (DMAs) comprising:

a notebook computer comprising;

a microprocessor;

a memory under the control of said microprocessor;

a system bus;

a central DMA controller in communication with said memory via said system bus, said central DMA controller storing configuration information which provides for control of direct accesses to said memory for selected devices in communication with said system bus; and

a peripheral unit which accesses said memory via said central DMA controller;

and

a docking station which communicates with said notebook computer via a connector, said docking station comprising;

a slave DMA controller in communication with said system bus via said connector, said slave DMA controller also in communication with said central DMA controller via a hardware connection, and wherein said hardware connection provides data to said central DMA controller which designates selected portions of said configuration information which is to be transferred to said slave DMA controller; and

a peripheral unit in communication with said memory via said slave DMA controller and said system bus.