Single crystal silicon dry-etch endpoint based on dopant-dependent and thermally-assisted etch rates

• US 5,591,300 A
• Filed: 06/07/1995
• Issued: 01/07/1997
• Est. Priority Date: 06/07/1995
• Status: Expired due to Fees

• Current Assignee: VTC, Inc. (Synaptics Incorporated)
• Original Assignee: VTC, Inc. (Synaptics Incorporated)
• Inventors: Schiller, Peter J.
• Primary Examiner(s): Breneman, R. Bruce
• Assistant Examiner(s): ALANKO, ANITA KAREN
• Application Number:
  US08/484,020
• Time in Patent Office: 580 Days
• Field of Search: 156/626.1, 156/628.1, 156/643.1
• US Class Current: 438/16
• CPC Class Codes: H01J 37/32935 Monitoring and controlling tubes by information coming from the object and/or discharge
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching

Abstract

A dry etching method for endpoint detection of a single crystal silicon wafer is disclosed. A top portion of the single crystal silicon wafer is doped with heavy levels of a doping agent, thereby creating heavily and lightly doped regions within the single crystal silicon wafer. A photoresist is patterned on the top surface of the single crystal silicon wafer and etching commences on the top surface. The etch rate is monitored as the etch progresses through the top portion of the single crystal silicon wafer to determine the etch endpoint. The etch endpoint is detected by a local minimum generated by the combined effects of wafer surface thermal heating and the change or etch rate between the heavily doped single crystal silicon and lightly doped single crystal silicon. Once the etch endpoint has been detected, the etching process is stopped, and the photoresist is removed, thereby exposing a doped product.

Claims

1. A process for detecting an endpoint in a dry etch process comprising:

monitoring the combination of a decreasing etch rate and an increasing surface thermal heating as the etch progresses between a heavily doped region of a single crystal silicon wafer and a lightly doped region of the single crystal silicon wafer; and

detecting a local minima of the effects of the decreasing etch rate and increasing surface thermal heating.

2. The method of claim 1, where the atomic concentration of he dotting agent in the heavily doped region of the single crystal silicon wafer is 0.5%.

3. The method of claim 1, where the atomic concentration of the doping agent in the lightly doped region of the single crystal silicon wafer is less than 0.01%.

4. The method of claim 1, where the doping agent is arsenic.

5. The method of claim 1, where the local minima is determined by a decreasing luminous intensity due to a decreasing etch rate and an increasing luminous intensity due to an increase in wafer surface thermal heating.

6. A dry etching process for forming a semi-conductor device comprising:

doping a top region of a single crystal silicon wafer with a doping agent such that the doping agent is interdispersed throughout a top portion of the single crystal silicon wafer, thereby forming a heavily doped top region and a lightly doped bottom region;

placing a photoresist on a portion of a top surface of the single crystal silicon wafer to protect a portion of the top surface and to expose a portion of the top surface;

etching the exposed portion of the top region of the single crystal silicon wafer;

detecting a local luminous intensity minimum through use of a combination of wafer surface thermal heating and a change of etch rate between the heavily doped top region and the lightly doped bottom region;

stopping the etching of the single crystal silicon wafer when the local minimum has been detected; and

lifting off the photoresist, thereby exposing a doped segment of the single crystal silicon wafer.

7. The method of claim 6, where the top region of the single crystal silicon wafer is heavily doped with the doping agent at an atomic concentration in the range of 0.1% to 2.0%.

8. The method of claim 6, where the bottom region of the single crystal silicon wafer contains the doping agent at an atomic concentration of less than 0.01%.

9. The method of claim 6, where the doping agent is arsenic.

10. The method of claim 6, further comprising:

placing the single crystal silicon wafer within a reaction chamber prior to doping; and

generating plasma in the reaction chamber after the photoresist has been placed on the portion of the top surface of the single crystal silicon wafer, thereby etching the exposed portion of the single crystal silicon wafer.

11. A dry etching process for forming a semi-conductor device comprising:

doping a top region of a single crystal silicon wafer with a doping agent such that the doping agent is interdispersed throughout a top portion of the single crystal silicon wafer, thereby forming a heavily doped top region and a lightly doped bottom region;

placing a photoresist on a portion of a top surface of the single crystal silicon wafer to protect a portion of the top surface and to expose a portion of the top surface;

etching the exposed portion of the top region of the single crystal silicon wafer;

detecting a local minimum through use of a combination of a decreasing luminous intensity due to a decreasing etch rate and an increasing luminous intensity due to an increase in wafer surface thermal heating;

stopping the etching of the single crystal silicon wafer when the local minimum has been detected; and

lifting off the photoresist, thereby exposing a doped segment of the single crystal silicon wafer.

12. The method of claim 11, where the top region of the single crystal silicon wafer is heavily doped with the doping agent at an atomic concentration in the range of 0.1% and 2.0%.

13. The method of claim 11, where the bottom region of the single crystal silicon wafer contains the doping agent at an atomic concentration of less than 0.01%.

14. The method of claim 11, where the doping agent is arsenic.

15. The method of claim 11, further comprising:

placing the single crystal silicon wafer within a reaction chamber prior to doping; and

generating plasma in the reaction chamber after the photoresist has been placed on the portion of the top surface of the single crystal silicon wafer, thereby etching the exposed portion of the single crystal silicon wafer.