Method of manufacturing flash memory with inclined channel region

• US 5,591,652 A
• Filed: 05/30/1995
• Issued: 01/07/1997
• Est. Priority Date: 11/08/1993
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Matsushita, Tadashi
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/452,695
• Time in Patent Office: 588 Days
• Field of Search: 437/35, 437/43, 437/48, 437/52
• US Class Current: 438/259
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel

Abstract

A electrically erasable and programmable memory comprising: a semiconductor substrate; a source region and a drain region formed spaced apart from each other by a definite distance on a main surface of said semiconductor substrate; a channel region provided between the source region and the drain region; a gate insulating film provided on the channel region; a floating gate electrode provided on the gate insulating film; and a control gate electrode provided with an interlayer insulating film sandwiched therebetween so that the control gate electrode at least partially laminates the floating gate electrode; the channel region and the main surface having an inclined portion and the source region being provided relatively above or below the drain region.

Claims

1. A method for forming a electrically erasable and programmable memory comprising the steps of:

forming a device isolation oxide film on a region of a main surface of a semiconductor substrate of a first conductivity type, the region being where a device isolation region is to be formed and a portion of an active region is to be formed;

removing an oxide film including part of the device isolation oxide film to form the portion of the active region, the portion of the active region having an inclined portion on a surface thereof;

forming a first gate insulating film on the inclined portion of the active region and a second gate insulating film on the active region except for the inclined portion;

forming a floating gate electrode on the first gate insulating film;

forming a third gate insulating film on the floating gate electrode;

forming a control gate electrode so that the control gate electrode is patterned in such a manner that the control gate at least partially overlies the floating gate electrode;

implanting impurity ions of a second conductivity type using the floating gate electrode as a mask thereby forming either a source region or a drain region where at least some of the device isolation oxide film has been removed.

2. A method according to claim 1 wherein the second gate insulating film is formed in a region having a surface impurity concentration of 3×

10²⁰ ions/cm³ or more and in a region having a concentration less than the surface impurity concentration.

3. A method according to claim 1 wherein the first gate insulating film and the second gate insulating film have different thicknesses.

4. A method according to claim 1 further comprising the steps of forming the device isolation oxide film by oxidation treatment over both the device isolation region and a part of the active region and removing the device isolation oxide film on the active region, thereby generating hot electrons in a portion of the substrate where the crystal structure has been disturbed by edge-stress generated by an oxidation treatment and at an end part of the drain region facing a channel region, and then injecting the hot electrons into the floating gate electrode.

5. A method according to claim 1 further comprising using the control gate as a mask for forming a low concentration diffusion layer (LDD) in one of the source and drain regions.

6. A method for forming a electrically erasable and programmable memory, the method comprising the steps of:

preparing a source region and a drain region in spaced-apart relation on a main surface of a semiconductor substrate;

providing a channel region between the source region and the drain region, at least a portion of the channel region being inclined so that the source region and the drain region are not vertically coextensive;

providing a gate insulating first film on the channel region;

forming a floating gate electrode on the gate insulating first film;

using the floating gate electrode as a mask for implanting impurity ions into at least one of the source region and the drain region.

7. The method of claim 6, further comprising:

forming a gate insulating second film on the floating gate electrode;

forming a control gate electrode on the gate insulating second film in such a manner that the control gate at least partially overlies the floating gate electrode;

using the control gate as a mask for forming a low concentration diffusion layer (LDD) in one of the source and drain regions.