Solid state imaging device with low trap density

• US 5,591,988 A
• Filed: 06/07/1995
• Issued: 01/07/1997
• Est. Priority Date: 03/23/1993
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd., TDK Corporation
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd., TDK Corporation
• Inventors: Kobori, Isamu, Yamauchi, Yukio, Arai, Michio, Takayama, Ichiro, Sakamoto, Naoya, Inushima, Takashi, Codama, Mitsufumi, Sugiura, Kazushi
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/477,104
• Time in Patent Office: 580 Days
• Field of Search: 257/59, 257/66, 257/72, 257/291, 257/292, 437/3, 437/4, 437/19, 437/174, 437/907, 437/908
• US Class Current: 257/59
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 31/1133 the device being a conductor-insulator-semiconductor diode or a CCD device

Abstract

A substrate (1) has a surface covered with an insulation layer (2), on which an active layer (3'"'"') made of non-single crystal silicon through thin film technique is provided. A gate electrode layer (5'"'"') is partially provided on said active layer through a gate insulation layer (4). Said active layer (3'"'"') is subject to injection of P-type or N-type impurities to provide an image sensor of MOS structure. Bias potential is applied to a gate electrode so that a circuit between a source and a drain is in an On state, so that input light through said substrate or said gate electrode is applied to said active layer, and electrical output depending upon said input light is obtained from said source electrode or said drain electrode. Other MOS transistors for switching element and/or shift registers for operating said image sensor are provided on said substrate (1). Said active layer (3'"'"') is obtained by crystallizing said amorphous silicon layer through a laser anneal process or a high temperature anneal process, and hydrogenation process, and the trap density of said active layer is less than 5×10¹¹ /cm². Optical response time is short, less than 500 μsec, so, high speed operation ten times as high as that of a prior image sensor is possible.

Claims

1. A solid state image sensor comprising;

a substrate having insulation surface,

an active layer of non-single crystal silicon layer provided on said insulation surface, having at least a source region and a drain region,

a gate electrode layer provided on light receiving region between said source region and said drain region on said active layer through a gate insulation layer,

a source electrode layer and a drain electrode layer each provided on said source region and said drain region, respectively,

trap density of said active layer being less than 5×

10¹¹ /cm²,

said gate electrode layer being provided a predetermined bias potential, and

electrical output of current between said source electrode layer and said drain electrode layer being provided depending upon input light which illuminates said light receiving region on said active layer.

2. A solid state image sensor according to claim 1, wherein said gate electrode layer is made of an Indium-Tin-Oxide, ITO, layer, and said input light is introduced to said light receiving region through said gate electrode layer.

3. a solid state image sensor according to claim 1, wherein said substrate is transparent for input light, and said input light is introduced to said light receiving region through said substrate.

4. a solid state image sensor according to claim 1, wherein said bias potential is determined so that a circuit between a source electrode and a drain electrode is in an ON state.

5. A solid state image sensor according to claim 1, wherein absolute value of said bias potential is less than 7.5 V.

6. A solid state image sensor according to claim 1, wherein said bias potential is determined so that a circuit between a source electrode and a drain electrode is in an OFF state.

7. A solid state image sensor according to claim 1, wherein said substrate is made of non-single crystal silicon.

8. A solid state image sensor according to claim 1, wherein said substrate is made of glass.

9. A solid state image sensor according to claim 1, wherein said active layer is a non-single crystal silicon layer which is obtained by crystallizing amorphous silicon layer through anneal process with a laser pulse and hydrogenation process.

10. A solid state image sensor according to claim 1, wherein a thickness of said active layer is in the range between 20 nm and 1000 nm, a thickness of said gate insulation layer is in the range between 20 nm and 300 nm, and said active layer is a non-single crystal silicon layer obtained by crystallizing said amorphous silicon layer through anneal process at higher than 600°

C., and hydrogenating the same.

11. A solid state image sensor according to claim 1, wherein said substrate mounts thin film MOS transistors for a switching element and a shift register for operating said image sensor.