×

Membrane dielectric isolation IC fabrication

  • US 5,592,018 A
  • Filed: 06/07/1995
  • Issued: 01/07/1997
  • Est. Priority Date: 04/08/1992
  • Status: Expired due to Term
First Claim
Patent Images

1. A dielectrically isolated integrated circuit formed by a method comprising the steps of:

  • providing a substrate having a principal surface;

    forming an etch barrier layer in the substrate parallel to the principal surface;

    forming the integrated circuit on the principal surface wherein the integrated circuit includes at least one transistor;

    depositing a low stress insulating membrane over the integrated circuit; and

    etching away to the etch barrier layer a portion of the substrate from a backside of the substrate opposite the integrated circuit;

    wherein the insulating membrane and remaining substrate containing the integrated circuit have a combined thickness less than about 50 μ

    m.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×