Integrated MOSgated power semiconductor device with high negative clamp voltage and fail safe operation

• US 5,592,117 A
• Filed: 04/11/1995
• Issued: 01/07/1997
• Est. Priority Date: 04/11/1995
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Nadd, Bruno C.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US08/420,194
• Time in Patent Office: 637 Days
• Field of Search: 327/108, 327/110, 327/318, 327/328, 327/365, 327/374, 327/376, 327/377, 327/379, 327/419, 327/427
• US Class Current: 327/374
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/08128 in composite switches
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches

Abstract

A high side switch having a MOSgated power device has a control circuit which contains a control MOSFET which is connected between the gate and source of the MOSgated power device. The input signal to turn the power device on and off is connected to a level translator circuit which is, in turn, connected to an inverter circuit which drives the gate of the control MOSFET. The control MOSFET then prevents the turn on of the power MOSFET during the turn-off process. A high negative clamp voltage causes a higher di/dt reduction of current during turn off to shorten the turn-off time. The power MOS device cannot be turned on whenever V_CC is low and the output voltage is negative.

Claims

1. A high side switch circuit comprising:

a voltage source (V_CC) terminal;

a logic ground terminal;

an output voltage terminal connectable to one side of a load, the load being connectable at its other side to a load ground terminal;

a MOSgated semiconductor power device having first and second power electrodes and a control electrode, said first power electrode coupled to said output voltage terminal and said second power electrode coupled to said V_CC terminal;

an input circuit which produces signals for turning said power device off or on;

a main control MOSFET connected between said first power electrode and said control electrode of said power device for turning off said power device when said main control MOSFET turns on;

a signal level translator circuit for maintaining a substantially constant control voltage until commutation of said MOSgated semiconductor power device is desired; and

an inverter circuit, said inverter circuit coupled to said input circuit and said signal level translator circuit, said signal level translator circuit being coupled to said main control MOSFET to turn off said main control MOSFET in response to an input turn-on signal, the threshold conduction voltage of said main control MOSFET being lower than the threshold conduction voltage of said MOSgated semiconductor power device.

2. The circuit of claim 1 wherein said MOSgated power device is a power MOSFET.

3. The circuit of claim 1 wherein said power device and said control MOSFET are N channel devices which are integrated into a common semiconductor chip, and wherein said inverter circuit and translator circuit are also integrated into said common semiconductor chip.

4. The circuit of claim 1, wherein said signal level translator circuit comprises a resistor and a second control MOSFET connected in series and having a node;

one end of said resistor connected to said logic ground terminal;

one end of said second MOSFET connected to said output voltage terminal;

said node between said resistor and said second MOSFET connected to the gate of said main control MOSFET;

said substantially constant control voltage being applied to the gate of said second control MOSFET.

5. The circuit of claim 4 which further includes a zener diode connected between the gate of said second control MOSFET and said output voltage terminal.

6. The circuit of claim 4 which further includes third MOSFET coupled between said gate of said power device through a limiting resistor and said logic ground terminal;

said input circuit being coupled to the gate of said third MOSFET means.

7. The circuit of claim 1 wherein said translator circuit comprises first and second identical translator MOSFETs and first and second identical translator resistors;

said first and second translator MOSFETs being connected in series with said first and second translator resistors respectively;

said first and second translator MOSFETs being connected to said output terminal;

said first translator resistor being connected to said logic ground terminal;

the node between said first translator MOSFET and first translator resistor connected to the gates of said first and second translator MOSFETs;

the node between said second translator MOSFET and said second translator resistor connected to the gate of a second control MOSFET;

said inverter circuit coupling said second translator resistor to said input circuit.

8. The circuit of claim 7 wherein said inverter circuit includes an inverter MOSFET in series with a pull-up resistor which is connected to said Vcc terminal;

the gate of said inverter MOSFET connected to said input circuit;

the node between said inverter MOSFET and said pull-up resistor connected to the base of a bipolar transistor; and

a zener diode connected between the emitter of said bipolar transistor and said second translator resistor.

9. The circuit of claim 7 which further includes third MOSFET coupled between said gate of said power device through a limiting resistor and said logic ground terminal;

said input circuit being coupled to the gate of said third MOSFET.

10. The circuit of claim 7, wherein said inverter circuit includes an inverter MOSFET in series with a pull-up resistor which is connected to said Vcc terminal;

the gate of said inverter MOSFET connected to said input circuit;

the node between said inverter MOSFET and said pull-up resistor connected to the base of a bipolar transistor; and

regulator means connected between the emitter of said bipolar transistor and said second translating resistor.

11. The circuit of claim 7, wherein said inverter circuit includes a first inverter MOSFET;

a second inverter MOSFET having an inverting gate terminal; and

a third inverter MOSFET, the gates of said first and second inverter MOSFETs being connected, the drain of said second inverter MOSFET being connected to said V_CC terminal, the source of said first inverter MOSFET being connected to said logic ground terminal, the source of said second inverter MOSFET being connected to the drains of said first and third inverter MOSFETs, the source of said second inverter MOSFET being further connected to the gate of said third inverter MOSFET, the source of said third inverter MOSFET being connected to said second translator resistor.