Modified bang-bang phase detector with ternary output

• US 5,592,125 A
• Filed: 08/18/1995
• Issued: 01/07/1997
• Est. Priority Date: 10/26/1994
• Status: Expired due to Term

• Current Assignee: Dot Assets No 12 LLC (Intellectual Ventures LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Williams, Bertrand J.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/516,917
• Time in Patent Office: 508 Days
• Field of Search: 331/1 A, 331/25, 327/12, 327/150, 327/159, 329/303, 329/310-313, 360/41, 360/51, 375/327, 375/328, 375/375, 375/376
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A phase detector is described. The phase detector receives a data signal from an external circuit. The phase detector generates a first signal when a transition edge of the clock signal occurs after a transition edge of the data signal. The phase detector generates a second signal when the transition edge of the clock signal occurs before the transition edge of the data signal and generates a third signal when the data signal remains in a same signal state for at least two transition edges of a same type of the clock signal.

Claims

1. A method for controlling a clock generator comprising:

generating a clock signal;

receiving a data signal from an external circuit;

generating a first polarity signal when a transition edge of said clock signal occurs after a transition edge of said data signal;

generating a second polarity signal when said transition edge of said clock signal occurs before said transition edge of said data signal; and

generating a presence signal when said data signal remains in a same signal state for at least two transition edges of a same type of said clock signal.

2. A method for controlling a clock generator comprising:

generating a clock signal;

receiving a data signal from an external circuit;

generating a first signal when a transition edge of said clock signal occurs after a transition edge of said data signal;

generating a second signal when said transition edge of said clock signal occurs before said transition edge of said data signal; and

generating a third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said clock signal, said third signal enabling one of said first and second signals to modify said clock signal, said first signal and said second signal representing, respectively, a first and a second state of a polarity function.

3. A method for controlling a clock generator comprising:

generating a clock signal;

receiving a data signal from an external circuit;

generating a signal having a first state, a second state and a third state, said first state occurring when a transition edge of said clock signal occurs after a transition edge of said data signal, said first state representing a first polarity value;

said second state occurring when said transition edge of said clock signal occurs before said transition edge of said data signal, said second state representing a second polarity value; and

said third state occurring when said data signal remains in a same signal state for at least two transition edges of a same type of said clock signal, said third state not modifying said clock signal.

4. A phase-locked loop circuit comprising:

a clock generator operable to accelerate a clock signal in response to a first signal, operable to delay said clock signal in response to a second signal, and operable to maintain said clock signal in response to a third signal;

a phase detector coupled to a said clock generator operable to generate said first signal when a transition edge of said clock signal occurs after a transition edge of a data signal, wherein said phase detector is operable to generate said second signal when said transition edge of said clock signal occurs before said transition edge of said data signal, and wherein said phase detector is operable to generate said third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said clock signal, said third signal enabling one of said first and second signals to modify said clock signal, said first signal and said second signal representing respectively a first and second state of a polarity function; and

a data input coupled to said phase detector allowing said phase detector to receive said data signal from an external circuit.