High resolution image processor with multiple bus architecture
First Claim
1. High resolution digital image storage and processing arrangement for capturing, storing, enhancing and displaying a series of video images produced by a high resolution video imager that delivers image signals having a density of 2048 lines per frame and for furnishing said video image signals to a high resolution image display device, comprising:
- a) A/D circuit means for converting said video image signals to a digital image signal as a sequence of digital bytes at a density of 2048 pixels per line of said video image signal;
b) display circuit means for providing said video image signal to said image display device including onboard memory means for temporarily storing at least one frame of said digital image signal, and buffering means for providing said video image signal to said display device at a frame rate independent of the frame rate of the digital image signal supplied to said display circuit means;
c) image processor circuit means including video memory means for storing at least one frame of said digital image signal and image enhancement means for creating an enhanced video image based on the digital image signal stored in said video memory means;
d) memory interface circuit means for writing frames of said digital image signal onto a bulk data storage medium and for reading frames of the digital image signal from said storage medium;
e) system controller means for generating control signals to control flow of said digital image signal between the A/D circuit means, said display circuit means, said image processor circuit means and said memory interface circuit means;
f) a user interface device permitting a user to select an operational mode, and means generating a control signal based on the operational mode selected;
g) a digital control bus coupled to said A/D circuit means, said display circuit means, said image processor circuit means, said memory interface circuit means, said system controller means and said user interface device for carrying control signals between said system controller means and said A/D circuit means, said display circuit means, said image processor circuit means, and said memory interface circuit means; and
h) a plurality of parallel independently addressable data buses each of which is coupled to a respective data bus interface on each of said A/D circuit means, said display circuit means, said image processor circuit means, and said memory interface circuit means.
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Accused Products
Abstract
A multiple video data bus architecture permits high speed data transfer among the various circuit elements of a fluoroscopic imaging processor. This permits simultaneous acquisition, storage, display, and image enhancement of high resolution, i.e., 2K×2K images. A memory interface circuit compresses the video data for storage in bulk memory. The processor supports several high-resolution monitors which can respectively display radiographic images from different subjects, so that review and diagnosis can occur remotely.
178 Citations
9 Claims
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1. High resolution digital image storage and processing arrangement for capturing, storing, enhancing and displaying a series of video images produced by a high resolution video imager that delivers image signals having a density of 2048 lines per frame and for furnishing said video image signals to a high resolution image display device, comprising:
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a) A/D circuit means for converting said video image signals to a digital image signal as a sequence of digital bytes at a density of 2048 pixels per line of said video image signal; b) display circuit means for providing said video image signal to said image display device including onboard memory means for temporarily storing at least one frame of said digital image signal, and buffering means for providing said video image signal to said display device at a frame rate independent of the frame rate of the digital image signal supplied to said display circuit means; c) image processor circuit means including video memory means for storing at least one frame of said digital image signal and image enhancement means for creating an enhanced video image based on the digital image signal stored in said video memory means; d) memory interface circuit means for writing frames of said digital image signal onto a bulk data storage medium and for reading frames of the digital image signal from said storage medium; e) system controller means for generating control signals to control flow of said digital image signal between the A/D circuit means, said display circuit means, said image processor circuit means and said memory interface circuit means; f) a user interface device permitting a user to select an operational mode, and means generating a control signal based on the operational mode selected; g) a digital control bus coupled to said A/D circuit means, said display circuit means, said image processor circuit means, said memory interface circuit means, said system controller means and said user interface device for carrying control signals between said system controller means and said A/D circuit means, said display circuit means, said image processor circuit means, and said memory interface circuit means; and h) a plurality of parallel independently addressable data buses each of which is coupled to a respective data bus interface on each of said A/D circuit means, said display circuit means, said image processor circuit means, and said memory interface circuit means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification