Programmable power generation circuit for flash EEPROM memory systems

• US 5,592,420 A
• Filed: 06/07/1995
• Issued: 01/07/1997
• Est. Priority Date: 10/17/1994
• Status: Expired due to Term

• Current Assignee: EMS Technologies, LLC (f/k/a Phoenix IP, LLC) (IPNav)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Cernea, Raul-Adrian, Lee, Douglas J., Mofidi, Mehrdad, Mehrotra, Sanjay
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/482,939
• Time in Patent Office: 580 Days
• Field of Search: 365/185.33, 365/185.18, 365/189.09, 365/226, 365/189.12
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp. The high current charge pump circuit is connected to relatively large off-chip charge storage devices, and the low current charge pump circuit is connected to relatively small on-chip charge storage devices. The controller may activate one or the other of the high or low current charge pump circuits through control signals connected to enabling circuitry respectively connected to the high and low current charge pump circuits. Alternatively, the controller may deactivate both the high and low current charge pump circuits and cause the high voltage Vpp to be provided from other circuitry on another flash EEPROM chip in the flash EEPROM module.

Claims

1. In a flash EEPROM chip having a plurality of flash EEPROM cells, a programmable voltage generator circuit comprising:

means for generating, in response to an enable signal, a high voltage and a high current from a low voltage source connected to said high voltage and high current generating means;

a plurality of registers respectively storing information indicative of a plurality of voltages suitable for programming, reading and erasing selected ones of said plurality of flash EEPROM cells; and

a plurality of digital-to-analog converters connected to said high voltage and high current generating means, wherein individual ones of said plurality of digital-to-analog converters are coupled to at least one of said plurality of registers to provide an analog output voltage proportional to the information stored in said at least one register.

2. The programmable voltage generator circuit as recited in claim 1, further comprising means for storing said information in said plurality of registers.

3. The programmable voltage generator circuit as recited in claim 2, wherein said means for storing information in said plurality of registers comprises:

a data latch;

a register address decoder; and

means including a controller for providing said data latch with information to be stored in a selected one of said plurality of registers, providing said register address decoder with information identifying said selected one of said plurality of registers, and causing said selected one of said plurality of registers to be enabled to receive and store said information provided to said data latch.

4. The programmable voltage generator circuit as recited in claim 1, further comprising a plurality of amplifiers, each amplifier connected to a respective one of said plurality of digital-to-analog converters and having a regulated voltage output indicative of the information stored in the at least one register connected to said respective one of said plurality of digital-to-analog converters.

5. The programmable voltage generator circuit as recited in claim 4, wherein said plurality of registers includes a bit line voltage register for storing information indicative of a bit line voltage suitable for programming selected ones of said plurality of flash EEPROM cells.

6. The programmable voltage generator circuit as recited in claim 4, wherein said plurality of registers includes a first control gate voltage register for storing information indicative of a word line voltage suitable for programming selected ones of said plurality of flash EEPROM cells, and a second control gate voltage register for storing information indicative of a word line voltage suitable for reading selected ones of said plurality of flash EEPROM cells.

7. The programmable voltage generator circuit as recited in claim 6, wherein said plurality of registers includes an erase gate voltage register for storing information indicative of a suitable erase gate voltage to be applied to the erase gates of selected ones of said plurality of flash EEPROM cells while reading said selected ones of said plurality of flash EEPROM cells.

8. In a flash EEPROM chip having a plurality of flash EEPROM cells, a programmable voltage generator circuit comprising:

means for generating, in response to an enable signal, a high voltage and a high current from a low voltage source connected to said high voltage and high current generating means;

a plurality of registers respectively storing information indicative of a plurality of voltages suitable for programming, reading and erasing selected ones of said plurality of flash EEPROM cells, wherein said plurality of registers includes a first control gate voltage register for storing information indicative of a word line voltage suitable for programming selected ones of said plurality of flash EEPROM cells, and a second control gate voltage register for storing information indicative of a word line voltage suitable for reading selected ones of said plurality of flash EEPROM cells;

a plurality of digital-to-analog converters connected to said high voltage and high current generating means, and each digital-to-analog converter respectively connected to at least one of said plurality of registers to provide an analog output voltage proportional to the information stored in said at least one register;

a plurality of amplifiers, each amplifier connected to a respective one of said plurality of digital-to-analog converters and having a regulated voltage output indicative of the information stored in the at least one register connected to said respective one of said plurality of digital-to-analog converters; and

means responsive to a program/verify mode control signal for passing, when said program/verify mode control signal is in a program state, said information stored in said first control gate voltage register to a digital-to-analog converter connected to said first and second control gate voltage registers through said passing means, and for passing, when said program/verify mode control signal is in a verify state, said information stored in said second control gate voltage register to said digital-to-analog converter connected to said first and second control gate voltage registers through said passing means.

9. The programmable voltage generator circuit as recited in claim 8, wherein the regulated voltage output of the amplifier connected to the digital-to-analog converter connected to said first control gate voltage register, provides a supply voltage to the amplifier connected to the digital-to-analog converter connected to said first and second control gate voltage registers through said passing means.

10. The programmable voltage generator circuit as recited in claim 8, further comprising means responsive to said information stored in said first control gate voltage register to control a slew rate of the amplifier connected to the digital-to-analog converter connected to said first and second control gate voltage registers through said passing means.

11. In a flash EEPROM chip having a plurality of flash EEPROM cells, a programmable voltage generator circuit comprising:

means for generating, in response to an enable signal, a high voltage and a high current from a low voltage source connected to said high voltage and high current generating means;

a plurality of registers respectively storing information indicative of a plurality of voltages suitable for programming, reading and erasing selected ones of said plurality of flash EEPROM cells, wherein said plurality of registers includes an erase gate voltage register for storing information indicative of a suitable erase gate voltage to be applied to the erase gates of selected ones of said plurality of flash EEPROM cells while reading said selected ones of said plurality of flash EEPROM cells;

a plurality of digital-to-analog converters connected to said high voltage and high current generating means, and each digital-to-analog converter respectively connected to at least one of said plurality of registers to provide an analog output voltage proportional to the information stored in said at least one register;

a plurality of amplifiers, each amplifier connected to a respective one of said plurality of digital-to-analog converters and having a regulated voltage output indicative of the information stored in the at least one register connected to said respective one of said plurality of digital-to-analog converters; and

a charge pump circuit responsive to an erase mode signal and an output of the digital-to-analog converter connected to said erase gate voltage register, for generating a suitable erase gate voltage to be applied to the erase gates of selected ones of said plurality of flash EEPROM cells while concurrently erasing said selected ones of said plurality of flash EEPROM cells.

12. The programmable voltage generator circuit as recited in claim 11, further comprising:

an amplifier connected between said charge pump circuit and said digital-to-analog converter connected to said erase gate voltage register; and

means responsive to information stored in said erase gate voltage register to control a slew rate of said amplifier connected between said charge pump circuit and said digital-to-analog converter connected to said erase gate voltage register.

13. An on-chip method of generating a plurality of voltages suitable for programming, reading or erasing a plurality of flash EEPROM cells, comprising the steps of:

respectively storing information indicative of said plurality of voltages in a plurality of registers;

respectively converting the information stored in said plurality of registers into a plurality of analog signals respectively proportional to the information stored in said plurality of registers; and

respectively generating said plurality of voltages by amplifying and regulating said plurality of analog signals.