Semiconductor memory having a sense amplifier with load transistors having different load characteristics

• US 5,592,427 A
• Filed: 06/06/1995
• Issued: 01/07/1997
• Est. Priority Date: 03/17/1993
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Kumakura, Sinsuke, Watanabe, Hisayoshi, Yamazaki, Hirokazu, Kasa, Yasushi
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US08/463,636
• Time in Patent Office: 581 Days
• Field of Search: 365/185.21, 365/205, 365/207, 365/208, 327/51
• US Class Current: 365/205
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Abstract

An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

Claims

1. A semiconductor memory having a sense amplifier comprising:

a load resistance section including a plurality of load transistors having different load characteristics which are selectable for connection; and

a load transistor select signal generating circuit for generating a select signal for selecting one of the plurality of load transistors for connection in accordance with a supply voltage supplied to said load resistance section.