Serial scan chain architecture for a data processing system and method of operation

• US 5,592,493 A
• Filed: 09/13/1994
• Issued: 01/07/1997
• Est. Priority Date: 09/13/1994
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Circello, Joseph C., Duerden, Richard, Crouch, Alfred L., Pressly, Matthew D.
• Primary Examiner(s): Nguyen, Hoa T.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/304,968
• Time in Patent Office: 847 Days
• Field of Search: 371/25, 371/22.3, 371/22.1, 371/22.4, 371/21.1, 371/25.1, 371/22.5, 371/22.6, 324/73 R
• US Class Current: 714/729
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test

Abstract

A scan chain architecture which has a controller (10), and a multiplexer (24) is used to route test data through functional units (12, 14, 16, 18, 20, and 22). The controller (10) receives as input a serial data stream from an STDI terminal and demultiplexes this data stream to one of the functional units (six functional units are illustrated in FIG. 1). Each of the functional units is considered as one scan chain and therefore FIG. 1 has six scan chains (one for each functional unit). In addition, a seventh scan chain couples all output flip-flops in each of the functional units together between an output of the MUX (24) and the STDO terminal/pin. Therefore, a serial scan of a data stream can be done through one functional unit, the multiplexer (24) and into the output flip-flops of each function unit to make testing easier to set-up. In addition, various new scan chain cells and low power methods are used herein.

Claims

1. A data processor having a scan chain architecture, the scan chain architecture comprising:

a plurality of scan chains wherein each scan chain in the plurality of scan chains has a plurality of serially connected storage elements, each scan chain having a first storage element which has a scan input and a last storage element which has a scan output;

a multiplexer having a plurality of inputs wherein each input in the plurality of inputs is coupled to one scan output from the plurality of scan chains, the multiplexer having a multiplexer output wherein the multiplexer output is selectively coupled to one of the inputs in the plurality of inputs via the multiplexer;

a demultiplexer having a plurality of outputs wherein each output in the plurality of outputs is coupled to one scan input from the plurality of scan chains, the demultiplexer having a demultiplexer input wherein the demultiplexer input is selectively coupled to one output in the plurality of outputs via the demultiplexer; and

an output scan chain having an input coupled to the output of the multiplexer and an output coupled to an output terminal of the data processor, the multiplexer serially coupling the output scan chain to a selected one of the plurality of scan chains to form a total scan chain comprising the selected one of the plurality of scan chains and the output scan chain.

2. The data processor of claim 1 wherein one of the scan chains in the plurality of scan chains is used to serially scan binary data for a circuit module selected from a group consisting of:

an operand cache unit, and instruction cache unit, a bus interface unit, an integer processing unit, and a floating point unit.

3. The data processor of claim 1 wherein the demultiplexer is part of a test controller which receives a plurality of test address signals wherein the plurality of test address signals selects one scan chain in the plurality of scan chains to receive a serial bit stream via a serial data input coupled to the demultiplexer input.

4. A data processor comprising:

a plurality of circuit modules;

a plurality of internal storage elements in each circuit module, the plurality of internal storage elements in each circuit module being connected in a serial manner to form an internal scan chain in each circuit module, each internal scan chain having an input and an output wherein the input of each internal scan chain is coupled to a test controller and the output of each internal scan chain is coupled to a multiplexer; and

a plurality of output storage elements in each circuit module, the plurality of output storage elements in each circuit module being different from the plurality of internal storage elements in each circuit module, the plurality of output storage elements in each circuit module being connected in a serial manner to form an output scan chain which is continuous through each circuit module, the output scan chain in each circuit module having an input and an output wherein the inputs and outputs of each of the output scan chains are coupled so that all the output scan chains in the circuit modules are coupled in a serial manner wherein the multiplexer selectively couples one internal scan chain and at least one output scan chain together in a serial manner to a scan data output terminal.

5. The data processor of claim 4 wherein the output scan chain comprises both output storage elements from the circuit modules and storage elements which are coupled to input and output terminals of the data processor.

6. The data processor of claim 4 wherein the test controller has a demultiplexer which is used to direct a serial bit stream from a serial input to one internal scan chain in the data processor.

7. The data processor of claim 6 wherein other internal scan chains which are different from the one internal scan chain in the data processor receive deasserted signals while the one internal scan chain in the data processor receives the serial bit stream, the deasserted signals being used in order to reduce power consumption in the data processor.

8. The data processor of claim 6 wherein other internal scan chains are kept in a serial shift mode to keep deasserted signals shifting through the other internal scan chains while the one internal scan chain in the data processor is functioning in a mode other than the serial shift mode.

9. The data processor of claim 4 wherein the test controller receives as input a serial data stream from an input terminal of an integrated circuit package which contains the data processor.

10. The data processor of claim 4 wherein the test controller receives as input a serial data stream from an the internal scan chains and routes the serial data stream to a terminal of an integrated circuit package which contains the data processor.

11. The data processor of claim 10 wherein the serial data stream is logically altered by a logic circuitry coupled to the multiplexer.

12. The data processor of claim 4 wherein the test controller receives as input an address which is used to select one internal scan chain among internal scan chains as a destination for a serial stream of input data.

13. The data processor of claim 4 wherein the output storage elements of a selected circuit module are time-sequential last storage elements in the circuit module which communicate signals external to the circuit module.

14. The data processor of claim 4 wherein the output storage elements of a selected circuit module are a set of last storage elements encountered within the selected circuit module before a signal exits the selected circuit module.

15. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output;

a first multiplexer having a first input coupled to receive a serial stream of data, a second input, a select input for receiving a select control signal, and an output coupled to the data input of the local storage element;

a second multiplexer having a first input coupled to the output of the local storage element, a second input coupled to a data input, a select input, and an output coupled to the first input of the first multiplexer; and

a logic gate having a first input for receiving an enable signal, a second input for receiving a speed path control signal, and an output coupled to the select input of the second multiplexer.

16. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output; and

a multiplexer having a first input coupled to receive a serial stream of data, a second input coupled to receive data signals, a select input for receiving a select control signal, and an output coupled to the data input of the local storage element.

17. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output;

a first multiplexer having a first input coupled to receive an enable signal, a second input, a select input for receiving a select control signal, and an output coupled to the data input of the local storage element; and

a second multiplexer having a first input coupled to the data output of the local storage element, a second input coupled to a data input, a select input coupled to a serial data input, and an output coupled to the first input of the first multiplexer.

18. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output; and

a logic gate for clearing a value stored in the local storage element.

19. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output;

a first multiplexer having a first input coupled to receive a serial stream of data, a second input, a select input for receiving a select control signal, and an output coupled to the data input of the local storage element;

a second multiplexer having a first input coupled to the output of the local storage element, a second input coupled to a data input, a select input coupled to a control signal, and an output coupled to provide output data; and

a third multiplexer having a first input coupled to the data input, a second input coupled to the data output of the storage element, a select input for receiving an output control signal, and an output coupled to the second input of the first multiplexer.

20. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output;

a first multiplexer having a first input coupled to receive a serial stream of data, a second input coupled to the data output of the local storage element, a select input for receiving a select control signal, and an output coupled to the data input of the local storage element; and

a second multiplexer having a first input coupled to a data input, a second input coupled to the output of the storage element, a select input for receiving an output control signal, and an output.

21. The data processor of claim 4 wherein a circuit module contains a memory wherein the memory has memory outputs, the memory outputs being coupled to memory storage elements wherein the memory storage elements are coupled in series and coupled within one output scan chain.

22. A data processor comprising:

a scan chain having a plurality of serially connected storage cells, each serially connected storage cell comprising;

a storage element having a clock input for receiving a clock signal, a data input, and a data output;

a first multiplexer having a first input coupled to receive a serial stream of data, a second input, a select input for receiving a select control signal, and an output coupled to the data input of the storage element;

a second multiplexer having a first input coupled to the output of the storage element, a second input coupled to a data input, a select input, and an output coupled to the first input of the first multiplexer; and

a logic gate having a first input for receiving an enable signal, a second input for receiving a speed path control signal, and an output coupled to the select input of the second multiplexer.

23. A method for providing a serial data stream to a data processor, the method comprising the steps of:

providing an address to a test controller, the address coupling one serial scan chain from a plurality of scan chains internal to the data processor to an input terminal, each scan chain in the plurality of scan chains having a plurality of serially connected storage elements, the serially connected storage elements of each scan chain defining a circuit module boundary wherein all the serially connected storage elements of each scan chain are within the circuit module boundary;

using the address to couple the one serial scan chain selectively to an output scan chain wherein the output scan chain is a serially connected plurality of storage elements from a plurality of different circuit modules defined by the circuit module boundaries; and

serially shifting the serial data stream into both the output scan chain and the one serial scan chain via the input terminal.

24. The method of claim 23 wherein the step of serially shifting comprises:

serially shifting deasserted values into an unselected serial scan chain, which is different from the one serial scan chain, while the serial data stream is being shifted into the one serial scan chain.

25. The method of claim 23 further comprising the step of:

placing the data processor into a serial shift mode to perform the step of serially shifting.

26. The method of claim 25 further comprising the step of:

placing the data processor into a parallel normal mode of operation after the step of serially shifting to alter a state of the data processor.

27. The method of claim 26 wherein the step of placing comprises:

serially shifting deasserted values into an unselected serial scan chain, which is different from the one serial scan chain, while the serial data stream is being shifted into the one serial scan chain; and

continuing to serially shift deasserted values into the unselected serial scan chain during a time that the one serial scan chain is operating in the parallel normal mode of operation.

28. The method of claim 23 wherein the step of serially shifting comprises:

reducing logic transitions in other serial scan chains which are not selected by the step of providing an address.