Common mode early voltage compensation subcircuit for current driver

• US 5,592,510 A
• Filed: 03/29/1994
• Issued: 01/07/1997
• Est. Priority Date: 03/29/1994
• Status: Expired due to Term

• Current Assignee: Apple Computer Incorporated (Apple Inc.)
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Van Brunt, Roger W., Oprescu, Florin A.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): VO, DON NGUYEN
• Application Number:
  US08/219,664
• Time in Patent Office: 1,015 Days
• Field of Search: 375/257, 375/219, 375/220, 326/62, 326/82, 326/86, 326/89, 326/90, 326/91
• US Class Current: 375/220
• CPC Class Codes: H03F 2203/45394 the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
• CPC Class Codes: H03F 2203/45592 the IC comprising one or more buffer stages other than emitter or source followers between the input signal leads and input leads of the dif amp, e.g. inverter stages
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45654 Controlling the active amplifying circuit of the differential amplifier
• CPC Class Codes: H03F 3/45766 by using balancing means
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/029 Provision of high-impedance states
• CPC Class Codes: H04L 5/20 using different combinations of lines, e.g. phantom working

Abstract

In a driver circuit for a twisted pair cable, a compensator for preventing appreciable common mode current flow into or out of the twisted pair cable in response to the device receiving a wide range of common mode voltage bias levels. A wide range of external bias voltages may be received as a result of variations in the ground node voltages of two coupled devices. The compensator circuit utilizes a feed back loop and monitors the bias voltage received on the twisted pair cable. As the magnitude of the common mode current increases due to external bias voltage variation from a reference bias voltage, the current flow of p-channel transistors, coupled in an arrangement of the present invention, is increased (or decreased, as necessary) so that reduced common mode current flows onto the twisted pair cable. The present invention reduces appreciable common mode current flow through the twisted pair cable from the driver that are due to variations in the external bias voltage between communication devices. The present invention provides high common mode output impedance for the driver circuit by altering the effective common mode common mode early voltage characteristics of the driver circuit while utilizing shorter channel length transistors for high speed communication capacity. The present invention also offers reduced current supply capacity of the common mode bias voltage source. The present invention operates ideally within driver circuits compatible with the IEEE P1394 communication standard.

Claims

1. A driver circuit comprising:

driving circuitry driving differential signals over a twisted pair cable and driving common mode current signals containing information over said twisted pair cable, said driving circuitry comprising driving transistors and having a bias voltage, said driving transistors coupled to said twisted pair cable; and

a subcircuit coupled to said driving circuitry and modifying an effective common mode early voltage characteristic of said driving transistors in response to variations in said bias voltage from a reference voltage level, said subcircuit effectively reducing common mode current flow over said twisted pair cable in response to variations of said bias voltage from said reference voltage level.

2. A driver circuit as described in claim 1 wherein said subcircuit is for increasing an effective output impedance of said driving transistors of said driving circuitry.

3. A driver circuit as described in claim 1 wherein said common mode current signals over said twisted pair cable are for conveying speed signal information.

4. A driver circuit as described in claim 1 wherein said subcircuit comprises two amplifiers coupled in a feedback arrangement.

5. A driver circuit as described in claim 1 wherein said driving transistors of said driving circuitry are current drivers.

6. A driver circuit as described in claim 1 wherein said driving transistors of said driving circuitry are small channel length p-type transistors.

7. A high speed current driver circuit comprising:

(a) a biased driver circuit driving differential and common mode current signals containing information over a twisted pair cable, said driver circuit driving high, low and null signals representative of digital information, said driver circuit comprising;

a first pair of transistors coupled to said twisted pair cable for driving differential signals;

a second pair of transistors coupled to said twisted pair cable for driving common mode signals; and

a third pair of transistors coupled to said twisted pair cable, said third pair of transistors for use in conjunction with said first pair and said second pair of transistors; and

(b) a common mode early voltage compensation circuit coupled to said biased driver circuit, said common mode early voltage compensation circuit monitoring a bias voltage level and minimizing common mode current flow over said twisted pair cable in response to variations of said bias voltage level from a reference bias voltage.

8. A high speed current driver as described in claim 7 wherein said common mode early voltage compensation circuit is for effectively increasing common mode early voltage characteristics of said first pair of transistors in response to said variations of said bias voltage level.

9. A high speed current driver as described in claim 8 wherein said first pair of transistors of said biased driver circuit are small channel length p-type transistors.

10. A high speed current driver as described in claim 8 wherein said common mode current signals are for conveying speed signal information.

11. A high speed current driver as described in claim 8 wherein said common mode early voltage compensation circuit comprises two amplifiers coupled in a feedback arrangement.

12. A driver circuit for communicating information over a twisted pair cable, said driver circuit comprising:

first circuitry for generating differential voltage signals over said twisted pair cable, said differential signals representative of binary data, said first circuitry having a bias voltage;

second circuitry for generating a common mode voltage signal over said twisted pair cable, said second circuitry responsive to a speed signal input, and said common mode voltage signal for indicating a high speed transmission rate; and

a common mode early voltage compensation circuit coupled to said first and second circuitry for monitoring said bias voltage and for minimizing common mode current flow over said twisted pair cable in response to variations of said bias voltage from a reference bias voltage level.

13. A driver circuit as described in claim 12 wherein said second circuitry is also for generating differential voltage signals over said twisted pair cable simultaneously with said common mode voltage signal.

14. A driver circuit as described in claim 12 wherein said common mode early voltage compensation circuit is for effectively increasing common mode early voltage characteristics of said first circuitry in response to said variations of said bias voltage.

15. A driver circuit as described in claim 14 wherein said first circuitry comprises p-type transistors of small channel length.

16. A driver circuit as described in claim 14 wherein said common mode early voltage compensation circuit comprises two amplifiers coupled in a feedback arrangement.

17. A driver circuit as described in claim 12 wherein said first circuitry is responsive to a set of inputs for generating high, low, and null differential voltage signals.

18. A driver circuit as described in claim 17 wherein said first circuitry comprises switchable current sources that are electrically coupled to or decoupled from said twisted pair cable in response to said set of inputs.

19. A driver circuit as described in claim 13 wherein said second circuitry is responsive to a set of inputs for generating said common mode voltage signal and also for generating high, low, and null differential voltage signals.

20. A driver circuit as described in claim 19 wherein said second circuitry comprises switchable current sources that are electrically coupled to or decoupled from said twisted pair cable in response to said set of inputs.

21. A driver circuit as described in claim 12 wherein said first circuitry and said second circuitry are implemented in CMOS technology on a single driver circuit.

22. A communication network comprising:

a plurality of communicating devices comprising a general purpose computer system, a digital graphic display device, a digital graphic input device, and a digital information storage device; and

associated with individual devices of said network, a driver circuit for communicating information over a twisted pair cable, said driver circuit comprising;

driving circuitry driving differential signals over said twisted pair cable and driving common mode current signals containing information over said twisted pair cable, said driving circuitry comprising driving transistors and having a bias voltage, said driving transistors coupled to said twisted pair cable; and

a subcircuit coupled to said driving circuitry and modifying an effective common mode early voltage characteristic of said driving transistors responsive to variations in said bias voltage from a reference voltage level, said subcircuit effectively reducing common mode current flow over said twisted pair cable in response to variations of when said bias voltage from said reference voltage level.

23. A communication network as described in claim 22 wherein said subcircuit is for increasing an effective output impedance of said driving transistors of said driving circuitry.

24. A communication network as described in claim 22 wherein said common mode current signals over said twisted pair cable are for conveying speed signal information.

25. A communication network as described in claim 22 wherein said subcircuit comprises two amplifiers coupled in a feedback arrangement.

26. A communication network as described in claim 22 wherein said driving transistors of said driving circuitry are current drivers.

27. A communication network as described in claim 22 wherein said driving transistors of said driving circuitry are small channel length p-type transistors.

28. In a communication device, a method of communicating information over a twisted pair cable, said method comprising the steps of:

generating differential voltage signals over said twisted pair cable, said differential voltage signals representative of digital information for transmission, said step of generating differential voltage signals performed by a single driver circuit;

generating common mode voltage signal over said twisted pair cable, said common mode voltage signal for signaling communication speed information, said step of generating common mode voltage signal also performed by said single driver circuit;

monitoring a bias voltage of said single driver circuit; and

minimizing common mode current flow over said twisted pair cable in response to variations of said bias voltage from a reference bias voltage level.

29. A method of communicating information as described in claim 28 wherein said step of minimizing common mode current flow over said twisted pair cable comprises the step of increasing a common mode early voltage characteristic of said single driver circuit in response to said variations of said bias voltage.

30. A method of communicating information as described in claim 28 wherein said steps of monitoring said bias voltage of said single driver circuit and minimizing common mode current flow over said twisted pair cable are implemented with amplifiers coupled in a feedback arrangement.

31. A method of communicating information as described in claim 28 wherein said step of generating differential voltage signals and said step of generating common mode voltage signal may be performed simultaneously over said twisted pair cable.

32. A method of communicating information as described in claim 28 further comprising the step of receiving a set of digital signal inputs for generating high, low and null differential voltage signals and wherein said step of generating differential voltage signals is responsive to said set of digital signal inputs.

33. A method of communicating information as described in claim 32 wherein said step of generating differential voltage signals utilizes switchable current sources that are electrically coupled to or decoupled from said twisted pair cable in response to said set of digital signal inputs.

34. A method of communicating information as described in claim 31 further comprising the step of receiving a set of digital signal inputs for generating said common mode voltage signal and also for generating high, low, and null differential voltage signals and wherein said step of generating said common mode voltage signal is responsive to said set of digital signal inputs.

35. A method of communicating information as described in claim 34 wherein said step of generating common mode voltage signal utilizes switchable current sources that are electrically coupled to or decoupled from said twisted pair cable in response to said set of digital signal inputs.