Fully digital data separator and frequency multiplier

• US 5,592,515 A
• Filed: 04/20/1995
• Issued: 01/07/1997
• Est. Priority Date: 04/01/1994
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Efendovich, Avner, Karpati, Varda, Shacham, Alon, Saban, Rami
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): Shankar, Vijay
• Application Number:
  US08/425,633
• Time in Patent Office: 628 Days
• Field of Search: 375/340, 375/359, 375/360, 375/371, 375/373, 375/375, 375/376, 327/156, 327/160, 327/166
• US Class Current: 375/340
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

The data separator of this invention may be used for extracting clock and data signals from a serial stream of bits read from a magnetic disk or tape. The data separator is supplied with a "fast" clock pulse generated by a frequency multiplexer. After a lock indication from the frequency multiplier, during the first eight serial data pulses the frequency and phase of the data separator are synchronized to the serial data pulses. Then an early and late logic unit keeps track digitally of the cumulative phase difference between the incoming data stream and the output of the data separator. When the cumulative phase difference reaches predetermined limits, the phase of the output is adjusted. If a second phase adjustment is required in the same direction (i.e., early or late), the frequency of the output is adjusted. The output of the data separator is generated by a decrementing register, the phase or frequency of the data separator being adjusted by increasing or decreasing the initial value loaded into the decrementing register. The data separator is fully digital.

Claims

1. A digital data separator comprising:

an early and late logic unit, said early and late logic unit comprising;

a phase shift accumulator (PSA) register having an input, said PSA register being actuated so as to change a binary value stored in said PSA register when a data input signal is phase-shifted with respect to a clock signal output, and

a limit detector connected to said PSA register, said limit detector detecting when the binary value stored in said PSA register reaches a predetermined limit;

a bit length register (BLR) logic unit, said BLR logic unit comprising a counter register, said counter register counting at a fast clock rate which is a preselected multiple of a data rate of said data input signal, an output from said limit detector causing a binary value to be loaded into said counter register; and

a counter oscillator, said counter oscillator receiving a detect signal when said counter register reaches a selected binary value and delivering said clock signal output.

2. The digital data separator of claim 1, said BLR logic unit further comprising a temporary bit length register for loading a binary value into said counter register in response to an output from said limit detector so as to phase-shift said clock signal output.

3. The digital data separator of claim 2, said BLR logic unit further comprising a bit length register, said bit length register for causing a binary value to be loaded into said counter register in response to an output of said limit detector so as to alter the frequency of said clock signal output.