Parallel frame synchronizer for detecting forward-ordered/reverse-ordered, inverted/non-inverted data

• US 5,592,518 A
• Filed: 03/28/1994
• Issued: 01/07/1997
• Est. Priority Date: 03/28/1994
• Status: Expired due to Term

• Current Assignee: OL Security LLC (Intellectual Ventures LLC)
• Original Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Inventors: Davis, Richard M., Genrich, Thad J., Hall, Mark W.
• Primary Examiner(s): COLES, EDWARD L
• Assistant Examiner(s): Esposo, Allan A.
• Application Number:
  US08/219,695
• Time in Patent Office: 1,016 Days
• Field of Search: 375/368, 375/365, 375/362, 375/364, 375/366, 375/354, 375/355, 375/371, 375/372, 370/105.1, 370/100.1, 370/102, 370/105.4, 370/106
• US Class Current: 375/368
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines

Abstract

A high speed parallel frame synchronizer provides high speed frame synchronization functions utilizing parallel processing techniques implemented with commercially available components. Serial input data is demultiplexed to an N bit wide word at a rate of 1/N of the input clock frequency. A total of N parallel correlators are used to detect the frame synchronization pattern. Outputs of the correlators are arbitrated using a priority encoder which provides synchronization information to the frame synchronizer. One embodiment of this invention utilizes 4N correlators to simultaneously provide for synchronization of true/inverted and forward/reverse data generated by real-time or playback data sources.

Claims

1. A method of detecting synchronizing to high speed serial true and inverted data capture by detecting a predetermined frame synchronization pattern within a received digital signal characterized by a serial bit stream, wherein a predetermined number of consecutive bits in the serial bit stream is converted to a parallel data word as the digital signal is received, the method comprising:

substantially simultaneously comparing each parallel data word with a plurality of predetermined parallel bit patterns, each bit pattern of the plurality of predetermined parallel bit patterns corresponding to a different representation of the frame synchronization pattern;

so as to characterize the digital signal being received and to determine a position of the frame synchronization pattern within the parallel data word, the digital signal being characterized as being one of the members of the group consisting of true forward, true reverse, inverted forward, and inverted reverse, wherein true forward is indicative of a forward-ordered, non-inverted bit sequences, true reverse is indicative of a reverse-ordered, non-inverted bit sequence, inverted forward is indicative of a forward-ordered, inverted bit sequence and inverted reverse is indicative of a reverse-ordered, inverted bit sequence;

generating a correlation signal for each substantially simultaneous comparison to indicate a degree of correlation between each of the plurality of predetermined parallel bit patterns and at least a portion of the parallel data word; and

selecting one of the correlation signals which has a degree of correlation greater than a predetermined minimum degree of correlation so as to detect the predetermined frame synchronization pattern.

2. The method of claim 1 wherein selecting one of the correlation signals comprises selecting a first received correlation signal with a degree of correlation greater than a predetermined minimum degree of correlation.

3. The method of claim 1 wherein a plurality of correlation signals are received simultaneously and wherein selecting one of the correlation signals comprises selecting one of the correlation signals according to a predetermined priority scheme.

4. The method of claim 1 further comprising storing the parallel data words in a memory so as to allow selective formatting of the parallel data words, the formatting being selected based on the characterization of the digital signal.

5. The method of claim 1 further comprising:

storing the parallel data words in a memory so as to allow selective formatting of the parallel data words, the formatting being selected based on the characterization of the digital signal; and

formatting the parallel data words so as to produce data words characterized as true forward.

6. The method of claim 5 wherein formatting the parallel data words includes retrieving the parallel data words from the memory in a sequence based upon the characterization of the digital signal so as to produce a forward ordered sequence of parallel data words.

7. The method of claim 5 wherein formatting the parallel data words includes reversing the sequence of the bits within each parallel data word.

8. The method of claim 5 wherein formatting the parallel data words includes inverting the bits within each parallel data word.

9. The method of claim 1 wherein the received digital signal is coded to induce a minimum number of state transitions to enhance signal detection, the method further comprising:

generating a plurality of parallel decoding patterns for decoding a corresponding sequence of parallel data words;

alternately selecting each of the plurality of parallel decoding patterns; and

combining the selected parallel decoding pattern with the corresponding parallel data word to decode the received digital signal.

10. The method of claim 9 further comprising repeating the steps of generating, selecting, and combining indefinitely while the digital signal is being received.

11. The method of claim 9 wherein generating a plurality of parallel decoding patterns includes, for each decoding pattern, linking outputs of a pattern generator with selected inputs of the pattern generator;

and

maintaining a current output state for a sufficient time to allow signals to propagate from the outputs of the pattern generator to the inputs of the pattern generator.

12. A system for detecting synchronizing to high speed serial true and inverted data capture by detecting a predetermined frame synchronization pattern within a received digital signal characterized by a serial bit stream, wherein a predetermined number of consecutive bits in the serial bit stream is converted to a parallel data word as the digital signal is received, the system comprising:

means for substantially simultaneously comparing each parallel data word with a plurality of predetermined parallel bit patterns, each bit pattern of the plurality of predetermined parallel bit patterns corresponding to a different representation of the frame synchronization pattern;

so as to characterize the digital signal being received and to determine a position of the frame synchronization pattern within the parallel data word, the digital signal being characterized as being one of the members of the group consisting of true forward, true reverse, inverted forward, and inverted reverse, wherein true forward is indicative of a forward-ordered, non-inverted bit sequences, true reverse is indicative of a reverse-ordered, non-inverted bit sequence, inverted forward is indicative of a forward-ordered, inverted bit sequence and inverted reverse is indicative of a reverse-ordered, inverted bit sequence;

means for generating a correlation signal for each substantially simultaneous comparison to indicate a degree of correlation between each of the plurality of predetermined parallel bit patterns and at least a portion of the parallel data word; and

means for selecting one of the correlation signals which has a degree of correlation greater than a predetermined minimum degree of correlation so as to detect the predetermined frame synchronization pattern.

13. The system of claim 12 wherein the means for selecting one of the correlation signals comprises means for selecting a first received correlation signal with a degree of correlation greater than a predetermined minimum degree of correlation.

14. The system of claim 12 wherein a plurality of correlation signals are received simultaneously and wherein the means for selecting one of the correlation signals comprises means for determining priority among the correlation signals and selecting the correlation signal with a highest priority.

15. The system of claim 12 further comprising a memory for storing the parallel data word so as to allow selective formatting of the parallel data word, the formatting being selected based on the characterization of the digital signal.

16. The system of claim 15 further comprising:

means for formatting the parallel data word so as to produce data words characterized as true forward.

17. The system of claim 16 wherein the means for formatting the parallel data word comprises:

means for retrieving the parallel data word from the memory in a selective sequence based upon the characterization of the digital signal;

means for selectively reversing the sequence of bits within each parallel data word based on the characterization of the digital signal; and

means for selectively inverting each bit of each parallel data word based on the characterization of the digital signal.

18. The system of claim 12 wherein the received digital signal is coded to induce a minimum number of state transitions to enhance signal detection, the system further comprising:

means for generating a plurality of parallel decoding patterns for decoding a corresponding sequence of parallel data words;

means for alternately selecting each of the plurality of parallel decoding patterns; and

means for combining the selected parallel decoding pattern with a corresponding parallel data word to decode the received digital signal.