Apparatus for providing shared virtual memory among interconnected computer nodes with minimal processor involvement
First Claim
1. Apparatus at a first node to update a first memory location, each said first node having at least one first processor, first operating system and first memory location with first virtual memory location address, said first node connected in a network to a plurality of second nodes, each said second node having at least one second processor, second operating system and second memory location having a second virtual memory location address, wherein said first memory location and said plurality of second memory locations contain shared memory values, each said first node having at least one page table containing virtual addresses and physical addresses of said first memory locations at said first node and of said second memory locations at said plurality of second nodes, comprising:
- (a) link hardware means at said first node for receiving a packet from said network containing an update value and said first virtual memory location address;
(b) means for accessing said at least one page table to translate said first virtual memory location address to a physical memory address corresponding to said first memory location; and
(c) means for updating, with said physical memory address, said first memory location with said update value;
whereby said receiving means and said updating means operate atomically independent of the operation of said first operating system.
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Accused Products
Abstract
The invention relates to general purpose interprocessor communication implemented through a distributed shared memory network connecting a plurality of processors, computers, multiprocessors, and electronic and optical devices. The invention teaches an apparatus for shared memory based data transfer between a multiplicity of asynchronously operating devices (processors, computers, multiprocessors, etc.) each using possibly distinct memory address translation architectures. The invention further teaches shared virtual memory network communication and administration based on a unique network memory address translation architecture. This architecture is compatible with and augments the address translation and cache block replacement mechanisms of existing devices. More particularly, the invention teaches an adapter card having input/output buffers, page tables and control/status registers for insertion into an operating device, or node, whereby all address translation, memory mapping and packet generation can be implemented. The invention teaches that all network activities can be completed with only write and control operations. An interconnecting switch part and bus arrangement facilitates communication among the network adapters.
167 Citations
6 Claims
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1. Apparatus at a first node to update a first memory location, each said first node having at least one first processor, first operating system and first memory location with first virtual memory location address, said first node connected in a network to a plurality of second nodes, each said second node having at least one second processor, second operating system and second memory location having a second virtual memory location address, wherein said first memory location and said plurality of second memory locations contain shared memory values, each said first node having at least one page table containing virtual addresses and physical addresses of said first memory locations at said first node and of said second memory locations at said plurality of second nodes, comprising:
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(a) link hardware means at said first node for receiving a packet from said network containing an update value and said first virtual memory location address; (b) means for accessing said at least one page table to translate said first virtual memory location address to a physical memory address corresponding to said first memory location; and (c) means for updating, with said physical memory address, said first memory location with said update value; whereby said receiving means and said updating means operate atomically independent of the operation of said first operating system.
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2. A system for updating shared memory comprising an apparatus at a first node to provide an update value to a plurality of second nodes, each said first node having at least one first processor, first operating system, and first memory location having a first virtual memory location address, said first node being connected in a network to a plurality of second nodes, each said second node having at least one second processor, second operating system and second memory location having a second virtual memory location address, wherein said first memory location and said plurality of second memory locations contain shared memory values, comprising:
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(a) link hardware means at said first node for receiving a first packet from said network containing an update value and said first virtual memory location address; and (b) updating means for updating with said first virtual memory location address and said first memory location; (c) a first page table means containing virtual addresses and physical addresses of said first memory locations at said first node and of said second memory locations at said plurality of second nodes for obtaining, based on said first virtual memory location address, at least one said second memory location address corresponding to said first virtual memory location address; and (d) generating means for generating a second packet containing said second memory location address and said update value; (e) sending means for sending said second packet to said plurality of second nodes; and whereby said generating means operates atomically independent of said first operating system. - View Dependent Claims (3)
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4. An apparatus for a first node to update a first memory location and to propagate a command based thereon to a network of nodes, each said first node having at least one first processor, first operating system and said first memory location with first virtual memory location address, said first node connected in a network to a plurality of second nodes, each said second node having at least one second processor, second operating system and second memory location having a second virtual memory location address, wherein said first memory location and said plurality of second memory locations contain shared memory values, said apparatus comprising:
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(a) first link hardware means for receiving at said first node a first network packet containing said update value and a first virtual memory location address; (b) updating means for updating said first memory location with said first virtual memory location address; (c) atomically generating means for atomically generating a command packet comprising at least one command based upon said update value; (d) sending means for sending said command packet to each said second node; (e) second link hardware means for receiving said command packet at each said second node; and (f) executing means for executing said command at each said second node; whereby said link hardware, said updating, said generating and said sending means operate atomically independent of operation of said first operating system, and said receiving and executing means operate atomically independent of the operation of said second operating system.
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5. An apparatus for updating shared virtual memory among shared memory locations having addresses, said shared memory locations being associated with a first node, said first node having a first operating system and at least one first page table, said shared memory locations also being associated with at least one second node, said second node connected to said first node through a network, and said second node having at least one second operating system and at least one second page table, said apparatus comprising:
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(a) memory mapping means for memory mapping said shared memory locations into said page tables; (b) multicasting means for multicasting a packet, containing at least one shared memory update and a virtual address for at least one said shared memory location, from said first node to said at least one second node; (c) link hardware means for receiving said packet at said at least one second node; (d) accessing means for accessing said at least one second page table; (e) page table means for finding said shared memory location corresponding to said virtual address at said at least one second node; and (f) updating means for updating said shared memory location at said at least one second node with said shared memory update; whereby said memory mapping means, said multicasting means, said link hardware means, said accessing means, said page table means and said updating means operate atomically independent of the operation of said first and said at least one second operating systems. - View Dependent Claims (6)
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Specification