Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system
First Claim
1. A defect-tolerant integrated circuit subsystem comprising:
- a plurality of modules comprising functional modules and one or more defective modules;
a hierarchical bus having a plurality of bus segments connecting to said modules;
a plurality of tri-stateable transceivers connected to the hierarchical bus for controlling signal transfer directions on said hierarchical bus and for preventing signal transfer on said hierarchical bus;
at least one bus master for controlling operation of said hierarchical bus, said at least one bus master being coupled to said plurality of tri-stateable transceivers; and
a plurality of programmable switches connected to the hierarchical bus for isolating said defective modules and defective bus segments of said hierarchical bus from a remainder of said subsystem.
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Abstract
A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (512K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) Use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) Use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the bus small; 5) Use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) use of programmable control register to facilitate run-time bus reconfiguration; 8) Use of spare bus lines to provide local redundancy for the bus; and 9) Use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained.
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Citations
15 Claims
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1. A defect-tolerant integrated circuit subsystem comprising:
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a plurality of modules comprising functional modules and one or more defective modules; a hierarchical bus having a plurality of bus segments connecting to said modules; a plurality of tri-stateable transceivers connected to the hierarchical bus for controlling signal transfer directions on said hierarchical bus and for preventing signal transfer on said hierarchical bus; at least one bus master for controlling operation of said hierarchical bus, said at least one bus master being coupled to said plurality of tri-stateable transceivers; and a plurality of programmable switches connected to the hierarchical bus for isolating said defective modules and defective bus segments of said hierarchical bus from a remainder of said subsystem. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification