Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system

• US 5,592,632 A
• Filed: 06/06/1995
• Issued: 01/07/1997
• Est. Priority Date: 11/05/1991
• Status: Expired due to Term

• Current Assignee: Mosys Incorporated (Peraso, Inc.)
• Original Assignee: Monolithic System Technology
• Inventors: Hsu, Fu-Chieh, Leung, Wing Y.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/469,887
• Time in Patent Office: 581 Days
• Field of Search: 395/306, 395/425, 395/575, 395/280, 395/182.01, 395/183.19, 371/8.1, 371/11.1, 371/40.1, 371/40.2, 365/200, 340/825.85
• US Class Current: 710/316
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1032 Simple parity
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 13/4077 Precharging or discharging
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/81 using a hierarchical redundancy scheme
• CPC Class Codes: G11C 29/832 with disconnection of faulty elements
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H04L 25/026 : Arrangements for coupling transmitters, receivers or transceivers to transmission lines; Line drivers duplexing arrangements H04L5/14
• CPC Class Codes: H04L 25/0272 : Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 : Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/029 : Provision of high-impedance states
• CPC Class Codes: H04L 25/0292 : Arrangements specific to the receiver end
• CPC Class Codes: H04L 5/1461 : Suppression of signals in the return path, i.e. bidirectional control circuits
• CPC Class Codes: Y10S 257/907 : Folded bit line dram configuration

Abstract

A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (512K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) Use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) Use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the bus small; 5) Use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) use of programmable control register to facilitate run-time bus reconfiguration; 8) Use of spare bus lines to provide local redundancy for the bus; and 9) Use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained.

Claims

1. A defect-tolerant integrated circuit subsystem comprising:

a plurality of modules comprising functional modules and one or more defective modules;

a hierarchical bus having a plurality of bus segments connecting to said modules;

a plurality of tri-stateable transceivers connected to the hierarchical bus for controlling signal transfer directions on said hierarchical bus and for preventing signal transfer on said hierarchical bus;

at least one bus master for controlling operation of said hierarchical bus, said at least one bus master being coupled to said plurality of tri-stateable transceivers; and

a plurality of programmable switches connected to the hierarchical bus for isolating said defective modules and defective bus segments of said hierarchical bus from a remainder of said subsystem.

2. The subsystem of claim 1, wherein at least one of said module comprises two identification registers for storing an identification code which uniquely identifies said at least one module.

3. The subsystem of claim 2, wherein said identification registers comprise a nonvolatile memory element and a software programmable register.

4. A defect-tolerant integrated circuit subsystem as in claim 3, wherein said nonvolatile memory element is programmed to store an identification code only if said at least one module is a functional module.

5. A defect-tolerant integrated circuit subsystem as in claim 3, wherein said software programmable register is written to during normal operation of the subsystem.

6. A defect-tolerant integrated circuit subsystem as in claim 3, further comprising means for transferring contents of the nonvolatile memory element to the software programmable register during a resetting of the subsystem.

7. The subsystem of claim 2, wherein said identification code is a base address for one or more memory blocks of said at least one module.

8. The subsystem of claim 1, wherein at least one of said modules comprises a control register having a programmable disable bit, which when set, causes said module to be disabled.

9. The subsystem of claim 1, wherein a plurality of said bus segments are arranged in a grid, said programmable switches being located at vertices of the grid.

10. The subsystem of claim 9, wherein said modules are coupled to said bus segments at a plurality of locations along the grid.

11. The subsystem of claim 10, wherein each module is coupled to the grid by one of the transceivers.

12. The subsystem of claim 11, wherein each of said modules is associated with one of a plurality of groups of said modules, each group of modules being coupled to the grid by one of the transceivers.

13. The subsystem of claim 9, wherein a plurality of said transceivers are located along the grid.

14. The subsystem of claim 13, wherein one of said transceivers is located between each adjacent pair of said programmable switches.

15. The subsystem of claim 14, wherein one or more of said modules is coupled to said grid between one of said transceivers and one of said programmable switches.