Method of forming contact pads for wafer level testing and burn-in of semiconductor dice

• US 5,593,903 A
• Filed: 03/04/1996
• Issued: 01/14/1997
• Est. Priority Date: 03/04/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Berman, Bernard, Lytle, William H., Beckenbaugh, William M.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/606,472
• Time in Patent Office: 316 Days
• Field of Search: 437/8, 437/51, 437/190, 437/226, 148/DIG. 28, 148/DIG. 162
• US Class Current: 438/18
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/05042 Si3N4
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method of forming contact pads (140) that allows for wafer level testing and burn-in of semiconductor die (22). A plurality of semiconductor die (22) are formed upon a semiconductor wafer (20), each semiconductor die (22) having a plurality of bonding pads (78). A contact pad (140) is formed overlying each bonding pad (78) and is electrically coupled to the bonding pad (78) and to wafer test pads (38) through vertical and/or horizontal wafer conductors (42-47 and 52-53 respectively) so that each semiconductor die (22) is uniquely identified. Contact pads (140) protect underlying bonding pads (78) during the formation and removal of vertical and/or horizontal wafer conductors (42-47 and 52-53 respectively). Thus, wafer level electrical testing and/or burn-in can be performed prior to designating a final packaging method for the semiconductor die (22).

Claims

1. A method for forming contact pads for wafer level testing of integrated circuit die comprising the steps of:

providing a semiconductor substrate having a plurality of integrated circuit die formed thereon, wherein each integrated circuit die has a plurality of bonding pads;

forming a conductive etch-barrier layer overlying and electrically coupled to the plurality of bonding pads; and

forming a conductive layer overlying the conductive etch-barrier layer, wherein the conductive layer is electrically coupled to the plurality of bonding pads, and whereby the conductive etch-barrier layer protects the plurality of bonding pads when the conductive layer is patterned and etched to form a contact pad overlying at least one of the plurality of bonding pads.

2. The method of claim 1, wherein the step of providing a semiconductor substrate further comprises forming an opening in a passivation layer wherein each of the plurality of bonding pads extends to an upper surface of the semiconductor substrate through said opening.

3. The method of claim 1, wherein the step of providing a semiconductor substrate further comprises forming the plurality of bonding pads from a metal comprising aluminum.

4. The method of claim 1, wherein the step of forming a conductive etch-barrier layer further comprises forming the conductive etch-barrier layer from a titanium-tungsten alloy.

5. The method of claim 1, wherein the step of forming a conductive layer further comprises forming the second conductive layer from a metal comprised of aluminum or copper.

6. The method of claim 1, further comprising the steps of:

patterning the conductive layer by etching to expose portions of the conductive etch-barrier layer; and

removing exposed portions of the conductive etch-barrier layer to form the contact pads.

7. The method of claim 6, wherein the step of patterning the conductive layer further comprises forming a pattern that includes a plurality of wafer test pads at a periphery of the semiconductor substrate, wherein the plurality of wafer test pads are electrically coupled to the contact pads such that each integrated circuit die is uniquely identified.

8. The method of claim 7, further comprising the step of performing a wafer level electrical test of the plurality of integrated circuit die.

9. The method of claim 8, wherein the step of performing a wafer level electrical test further comprises a wafer level burn-in.

10. The method of claim 6, further comprising the steps of:

removing the conductive layer;

removing the conductive etch-barrier layer; and

singulating the plurality of integrated circuit die, wherein each integrated circuit die is suitable for wire bonding or forming conductive bumps.

11. The method of claim 6, further comprising the steps of:

removing the conductive layer;

removing portions of the conductive etch-barrier layer not overlying the bonding pads;

forming conductive bumps overlying the conductive etch-barrier layer, wherein said conductive bumps are electrically coupled to the bonding pads; and

singulating the plurality of integrated circuit die.

12. The method of claim 6, further comprising the steps of:

removing portions of the conductive layer and the conductive etch-barrier layer, wherein unremoved portions of the conductive layer and the conductive etch-barrier layer overlie the plurality of bonding pads;

forming conductive bumps overlying the conductive layer, wherein said conductive bumps are electrically coupled to the bonding pads; and

singulating the plurality of integrated circuit die.

13. A method of manufacturing integrated circuit die that have been tested at the wafer level comprising the steps of:

providing a semiconductor substrate having a plurality of integrated circuit die formed thereon, wherein each integrated circuit die has a plurality of bonding pads extending to an upper surface of the semiconductor substrate;

forming a etch-barrier layer overlying the upper surface, wherein the etch-barrier layer is electrically coupled to the plurality of bonding pads;

forming a conductive layer overlying the etch-barrier layer, wherein the conductive layer is electrically coupled to the plurality of bonding pads;

patterning the conductive layer and the etch-barrier layer such that each integrated circuit die is uniquely electrically coupled;

electrically testing the plurality of integrated circuit die;

removing at least a portion of the conductive layer; and

removing at least a portion of the etch-barrier layer.

14. The method as in claim 13, wherein the step of patterning the conductive layer and the etch-barrier layer further comprises forming a plurality of wafer test pads.

15. The method as in claim 14, wherein the step of forming a plurality of wafer test pads further comprises forming the wafer test pads at a peripheral edge of the upper surface.

16. The method as in claim 13, wherein the step of electrically testing the plurality of integrated circuit die further comprises performing an electrical burn-in.

17. The method as in claim 13, wherein the step of electrically testing the plurality of integrated circuit die, further comprises performing a functionality test for each of the plurality of integrated circuit die.

18. The method as in claim 13, wherein the step of patterning the conductive layer and the etch-barrier layer, further comprises the steps of:

depositing and patterning a layer of photoresist to expose selected portions of the conductive layer;

removing selected portions of the conductive layer to expose portions of the etch-barrier layer; and

removing exposed portions of the etch-barrier layer, wherein remaining portions of the conductive layer are essentially unperturbed.

19. The method as in claim 13, wherein the step of removing at least a portion of the conductive layer, further comprises the steps of:

depositing a layer of photoresist over the conductive layer;

patterning the layer of photoresist to protect portions of the conductive layer overlying the plurality of bonding pads; and

etching unprotected portions of the conductive layer to expose portions of the etch-barrier layer.

20. The method as in claim 13, wherein the step of forming a conductive layer comprises forming a layer comprised of copper or aluminum.

21. The method as in claim 13, further comprising the step of forming a plurality of conductive bumps overlying the plurality of bonding pads, wherein each of the plurality of conductive bumps is uniquely electrically coupled to an underlying contact area.

22. The method as in claim 13, further comprising the step of singulating each of the plurality of integrated circuit die.