Method for fabricating a MOS transistor having an offset resistance

• US 5,593,909 A
• Filed: 06/06/1995
• Issued: 01/14/1997
• Est. Priority Date: 06/25/1993
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Han, Min-Koo, Min, Byung-Hyuk
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/467,715
• Time in Patent Office: 588 Days
• Field of Search: 437/40 GS, 437/41 GS, 437/44, 437/45, 437/29, 437/35, 437/48, 437/21
• US Class Current: 438/306
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A method for fabricating a MOS transistor having an offset resistance in a channel region controlled by a gate voltage and structure thereof is disclosed. A gate electrode is divided into three adjacent regions of respectively a second conductivity type, first conductivity type and second conductivity type connected laterally to one another on a channel region. A gate control voltage is applied to a central region of the first conductivity type, and a predetermined voltage between maximum and minimum values of the gate control voltage is applied to left and right adjacent regions of the second conductivity type. If a gate turn-on voltage is applied to the central region the gate turn-on voltage is forward biased to the adjacent left and right regions and is therefore also applied to the forwardly biased left and right regions. The effective length of the gate electrode then becomes the total length of the central region and the left and right adjacent regions. If a gate turn-off voltage is applied to the central region the central region becomes reverse biased with the and left and right adjacent regions and thus the effective length of the gate electrode becomes the length of only the central region of the first conductivity type. This reduces the length of the channel region, and thus forms an offset resistance structure which reduces leakage current in the off state of the MOS transistor.

Claims

1. A method for manufacturing a metal oxide semiconductor transistor having an offset resistance when turned off, comprising the steps of:

forming a gate insulation layer on an active region of a substrate;

forming a gate electrode on said gate insulation layer;

forming a first photoresist pattern on said gate electrode having a central portion of said gate electrode exposed;

implanting first ions of a first conductivity type into said central portion of said gate electrode using said first photoresist pattern as a first mask;

removing said first photoresist pattern;

forming a second photoresist pattern on said central portion of said gate electrode;

implanting second ions of a second conductivity type onto opposite portions of said gate electrode adjacent said central portion using said second photoresist pattern as a second mask; and

removing said second photoresist pattern.

2. The method for manufacturing a metal oxide semiconductor transistor having an offset resistance when turned off according to claim 1, wherein:

said step of forming said first photoresist pattern includes a step of forming said first photoresist pattern having opposite outer edge portions of said gate electrode exposed, said opposite outer edge portions being separate from said central portion; and

said step of implanting said first ions of said first conductivity type includes a step of implanting said first ions of said first conductivity type into said outer edge portions of said gate electrode.

3. The method for manufacturing a metal oxide semiconductor transistor having an offset resistance when turned off according to claim 1 wherein said step of implanting said second ions of said second conductivity type implants said second ions which have a conductivity type opposite said first conductivity type.

4. The method for manufacturing a metal oxide semiconductor transistor having an offset resistance when turned off according to claim 3 wherein said first conductivity type is a P-type semiconductor material and said second conductivity type is an N-type semiconductor material.

5. The method for manufacturing a metal oxide semiconductor transistor having an offset resistance when turned off according to claim 2 wherein said step of implanting said second ions of said second conductivity type implants said second ions which have a conductivity type opposite said first conductivity type.

6. The method for manufacturing a metal oxide semiconductor transistor having an offset resistance when turned off according to claim 5 wherein said first conductivity type is a P-type semiconductor material and said second conductivity type is an N-type semiconductor material.