SOI trench DRAM cell for 256 MB DRAM and beyond

• US 5,593,912 A
• Filed: 10/06/1994
• Issued: 01/14/1997
• Est. Priority Date: 10/06/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rajeevakumar, Thekkemadathil V.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/319,833
• Time in Patent Office: 831 Days
• Field of Search: 437/26, 437/47, 437/48, 437/52, 437/60, 437/203, 437/238, 257/301
• US Class Current: 438/696
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

A trench SOI structure is described. The structure is useful, for instance in the fabrication of DRAM cells. The structure can be fabricated by extending the conventional substrate plate trench cell. The SOI cell eliminates the parasitic trench sidewall leakage, reduces soft errors, eliminates well to substrate leakage, in addition to all the other advantages of SOI devices.

Claims

1. A method for fabricating a silicon-on-insulator ("SOI") trench structure, comprising:

providing an SOI substrate having an insulator layer and a silicon layer on the insulator layer;

etching a trench in the substrate, the trench extending through the silicon layer into the insulator layer;

forming an oxide layer on the walls of the trench;

forming a first masking layer on the oxide layer in the trench;

removing the first masking layer from an upper portion of the trench above the insulator layer, and leaving a remaining portion of the masking layer in a lower portion of the trench;

forming a second masking layer on the remaining portion of the first masking layer and on a part of the trench above the remaining portion of the first masking layer;

forming a masking collar on the upper portion of the trench above the second masking layer;

removing the second masking layer to expose a band of the trench between the masking collar and the first masking layer;

oxidizing the exposed band of the trench to form an annular oxide region in the substrate below the surface thereof.

2. The method of claim 1, wherein the masking collar comprises nitride.

3. The method of claim 1, wherein the first masking layer comprises nitride.

4. The method of claim 1, further comprising:

removing the masking collar and the remaining portion of the first masking layer;

forming a thin nitride layer on the trench wall surfaces;

extending the depth of the trench.

5. A method for fabricating a silicon-on-insulator ("SOI") trench structure, comprising:

providing an SOI substrate having an insulator layer and a silicon layer on the insulator layer;

etching a trench in the substrate, the extending through the silicon layer into the insulator layer;

forming an oxide layer on the walls of the trench;

forming a nitride masking layer on the oxide layer in the trench;

removing the nitride masking layer from an upper portion of the trench above the insulator layer, and leaving a remaining portion of the masking layer in a lower portion of the trench;

forming a second masking layer on the remaining portion of the nitride masking layer and on part of the trench above the remaining portion of the nitride masking layer;

forming a nitride masking collar on the upper portion of the trench above the second masking layer;

removing the second masking layer to expose a band of the trench between the masking collar and the nitride masking layer;

oxidizing the exposed band of the trench to form an annular oxide region in the substrate below the surface thereof;

removing the masking collar and the remaining portion of the nitride masking layer;

forming a thin nitride layer on the trench wall surfaces;

extending the depth of the trench.