Method of forming vias

• US 5,593,921 A
• Filed: 05/09/1995
• Issued: 01/14/1997
• Est. Priority Date: 09/23/1991
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Chen, Fusen E., Dixit, Girish A., Liou, Fu-Tai
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): EVERHART, CARIDAD
• Application Number:
  US08/438,167
• Time in Patent Office: 616 Days
• Field of Search: 437/195, 437/235, 437/238, 437/978, 437/228, 148/DIG. 43, 148/DIG. 118, 156/657.1
• US Class Current: 438/624
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: Y10S 148/043 Dual dielectric
• CPC Class Codes: Y10S 148/118 Oxide films

Abstract

A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.

Claims

1. A method of forming a via in a semiconductor integrated circuit, comprising the steps of:

forming a conductive structure over portions of an underlying region;

forming a conformal oxide layer over the conductive structure and the underlying region;

forming a planarizing oxide layer over the conformal oxide layer;

etching back the planarizing oxide layer to expose a portion of the conformal oxide layer over the conductive structure;

forming a metal oxide layer over the planarizing oxide layer and the exposed portion of the conformal oxide layer;

forming and patterning a resist layer over the metal oxide layer to define a selected via region;

etching the metal oxide layer to remove it from the selected via region, wherein the metal oxide etch is performed so as to selectively etch the metal oxide layer over the underlying conformal oxide layer;

etching the conformal oxide layer to remove it from the selected via region, wherein the conformal oxide etch is performed so as to selectively etch the conformal oxide layer over the metal oxide layer;

removing the resist layer; and

forming an upper interconnect structure over the metal oxide layer and extending into the via to contact the conductive structure.

2. The method of claim 1, wherein the conductive structure comprises a metal interconnect layer.

3. The method of claim 1, wherein the upper interconnect structure comprises a metal interconnect later.

4. The method of claim 1, wherein the conformal oxide layer has a thickness of at least approximately 5000 angstroms.

5. The method of claim 1, wherein the planarizing oxide layer comprises a spin-on-glass layer.

6. The method of claim 1, wherein the planarizing oxide layer has a thickness of between approximately 3000 to 5000 angstroms before the etchback step.

7. The method of claim 1, wherein the metal oxide layer has thickness of approximately 5000 angstroms.

8. The method of claim 1, wherein the metal oxide layer is a refractory metal oxide.

9. The method of claim 1, wherein the metal oxide layer is an aluminum oxide.

10. The method of claim 1, wherein the etching back step also removes a portion of the conformal oxide layer.

11. The method of claim 1, wherein the conformal oxide layer and the planarizing oxide layer etch at approximately the same rate during the etchback step.

12. The method of claim 1, wherein the via has a width greater than a width of the conductive structure.