Method of manufacturing semiconductor device

• US 5,593,926 A
• Filed: 10/07/1994
• Issued: 01/14/1997
• Est. Priority Date: 10/12/1993
• Status: Expired due to Fees

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Fujihira, Mitsuaki
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/319,546
• Time in Patent Office: 830 Days
• Field of Search: 437/209, 437/210, 437/211, 437/212, 437/213, 437/214, 437/226, 437/227, 148/DIG. 28
• US Class Current: 438/114
• CPC Class Codes: H01L 21/67023 for general liquid treatment, e.g. etching followed by cleaning
• CPC Class Codes: H01L 21/67126 Apparatus for sealing, encapsulating, glassing, decapsulating or the like processes H01L23/02, H01L23/28
• CPC Class Codes: H01L 21/67138 Apparatus for wiring semiconductor or solid state device
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/83855 Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/28 : Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01094 : Plutonium [Pu]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0695 : Polyamide
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/20105 : Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y10S 148/028 : Dicing

Abstract

A method of manufacturing a semiconductor device having a package including a base, and a chip mounted on the base, wherein the chip has a surface on which an element is formed, the method comprising the steps of (a) fixing the chip having a protective coat formed on the surface to the base; and (b) removing the protective coat from the chip without touching the chip.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

(a) forming first, second, and third wiring layers on a surface of a wafer, wherein said third wiring layer is arranged between said first and said second wiring layers;

(b) coating surfaces of said first, second, and third wiring layers and a remaining exposed surface of said wafer with a resist;

(c) partially removing said resist to expose a part of the surfaces of said first and second wiring layers;

(d) coating said exposed surfaces of said first and second wiring layers, and a surface of said resist, with a fourth wiring layer to connect said first wiring layer to said second wiring layer via said fourth wiring layer;

(e) removing said resist arranged between said fourth wiring layer and said third wiring layer to form an air gap between said third and fourth wiring layers, thereby forming an air bridge structure;

(f) forming a chip from said wafer having said air bridge structure, said chip being covered with a protective coat;

(g) die bonding said chip having said protective coat to a package; and

(h) removing said protective coat from said chip while keeping said chip fixed on said package.

2. A method according to claim 1, wherein said step (f) comprises the steps of:

adhering said wafer on an adhesive tape;

coating a surface of said wafer with said protective coat;

dicing said wafer to form said chip, while keeping said protective coat thereon; and

detaching said chip, coated with said protective coat, from said adhesive tape.

3. A method according to claim 1, wherein step (h) is performed by soaking said package in a solvent together with said chip, said solvent dissolving said protective coat.

4. A method according to claim 1, further comprising the step of drying said chip and said package by heating said base at a pressure lower than atmospheric pressure.

5. A method of manufacturing a semiconductor device, comprising the steps of:

(a) forming first, second, and third wiring layers on a surface of a wafer, wherein said third wiring layer is arranged between said first and said second wiring layers;

(b) coating surfaces of said first, second, and third wiring layers and a remaining exposed surface of said wafer with a resist;

(c) partially removing said resist to expose a part of the surfaces of said first and second wiring layers;

(d) coating said exposed surfaces of said first and second wiring layers, and a surface of said resist with a fourth wiring layer to connect said first wiring layer to said second wiring layer via said fourth wiring layer;

(e) removing said resist arranged between said fourth wiring layer and said third wiring layer to form an air gap between said third and fourth wiring layers, thereby forming an air bridge structure on said wafer;

(f) forming a chip from said wafer having said air bridge structure, said chip being covered with a protective coat;

(g) fixing said chip, having a surface coated with said protective coat, to a base;

(h) removing said protective coat from said chip while keeping said chip fixed on said base; and

(i) fixing said base to a package.

6. A method according to claim 5, wherein said step (f) comprises the steps of:

adhering said wafer on an adhesive tape;

coating a surface of said wafer with said protective coat;

dicing said wafer to form said chip, while keeping said protective coat thereon; and

detaching said chip, coated with said protective coat, from said adhesive tape.

7. A method according to claim 5, wherein step (h) is performed by soaking said base in a solvent together with said chip, said solvent dissolving said protective coat.

8. A method according to claim 5, further comprising the step of drying said chip and said base by heating said base at a pressure lower than atmospheric pressure.