Input protection circuit formed in a semiconductor substrate

• US 5,594,265 A
• Filed: 11/27/1991
• Issued: 01/14/1997
• Est. Priority Date: 11/30/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Wada, Masaharu, Numata, Kenji, Shimizu, Mitsuru, Fujii, Syuso
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/799,342
• Time in Patent Office: 1,875 Days
• Field of Search: 357/23.6, 357/23.13, 357/47, 357/48, 257/355, 257/356, 257/357, 257/358, 257/359, 257/360, 257/361, 257/362, 257/363
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

According to the invention, a well region is formed on a semiconductor substrate. An n⁺ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N⁺ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p⁺ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in a part of a surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region and connected to an input pad for receiving an external signal;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of the first semiconductor region in the surface region of said well region, said second semiconductor regions being connected to a ground potential; and

a third semiconductor region of the second conductivity type formed entirely within the surface region of said well region and connected to the ground potential, said third semiconductor region being arranged around said second semiconductor regions, wherein each of said second semiconductor regions contacts said third semiconductor region;

wherein said first semiconductor region, said well region, and said second semiconductor regions form a parasitic bipolar transistor between said input pad and the ground potential, and said first semiconductor region, said well region, and said third semiconductor region form a parasitic diode in parallel with said parasitic bipolar transistor between said input pad and the ground potential, and

wherein said well region includes no semiconductor region other than said first, second, and third semiconductor regions and is formed independently of other semiconductor circuits arranged in said semiconductor substrate.

2. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a first well region of a second conductivity type formed in a first part of a surface region of said semiconductor substrate;

a memory circuit formed in said first well region;

a second well region of the second conductivity type formed in a second part of the surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said second well region, said first semiconductor region being connected to an input pad for receiving an external signal and to an input circuit for supplying the external signal to said memory circuit formed in said first well region;

a second semiconductor region of the first conductivity type formed in the surface region of said second well region and formed near said first semiconductor region, said second semiconductor region being connected to a ground potential; and

a third semiconductor region of the second conductivity type formed entirely within the surface region of said second well region on a side of said second semiconductor region opposite to a side on which said first semiconductor region is formed, said third semiconductor region being connected to the ground potential.

3. A device according to claim 2, wherein said second well region includes no semiconductor region other than said first, second and third semiconductor regions.

4. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in a part of a surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region, said first semiconductor region being connected to an input pad for receiving an external signal;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in the surface region of said well region; and

a third semiconductor region of the second conductivity type formed in the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions,

wherein said well region includes no semiconductor region other than said first, second, and third semiconductor regions and is formed independently of other semiconductor circuits arranged in said semiconductor substrate, said second semiconductor regions are connected to a first potential, and said third semiconductor region is connected to a second potential lower than the first potential, and

wherein said first semiconductor region, said well region, and said second semiconductor regions form a parasitic bipolar transistor between said input pad and the first potential, and said first semiconductor region, said well region, and said third semiconductor region form a parasitic diode between said input pad and the second potential.

5. A device according to claim 4, wherein the first potential is a ground potential, and the second potential is a back gate bias potential.

6. A device according to claim 5, wherein the back gate bias potential is connected to said third semiconductor region through a resistor element.

7. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in a part of a surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region, said first semiconductor region being connected to an input pad for receiving an external signal;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in the surface region of said well region; and

a third semiconductor region of the second conductivity type formed in the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions,

wherein said well region includes no semiconductor region other than said first, second, and third semiconductor regions and is formed independently of other semiconductor circuits arranged in said semiconductor substrate, said second semiconductor regions are connected to a ground potential, said third semiconductor region is connected to a first back gate bias potential lower than the ground potential, and said semiconductor substrate is connected to a second back gate bias potential different from the first back gate bias potential, and

wherein said first semiconductor region, said well region, and said second semiconductor regions form a parasitic bipolar transistor between said input pad and the ground potential, and said first semiconductor region, said well region, and said third semiconductor region form a parasitic diode between said input pad and the first back gate bias potential.

8. A device according to claim 7, further comprising first and second potential generating circuits, arranged on said semiconductor substrate, for respectively generating the first and second back gate bias potentials.

9. A device according to claim 7, wherein the first conductivity type is an n type, and the second conductivity type is a p type.

10. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in a part of a surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region and connected to an input pad for receiving an external signal;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of the first semiconductor region in the surface region of said well region; and

a third semiconductor region of the second conductivity type formed entirely within the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions and said second semiconductor regions being in contact with said third semiconductor region, said second semiconductor regions and said third semiconductor region being connected to a ground potential,

wherein said well region includes no semiconductor region other than said first, second, and third semiconductor regions and is formed independently of other semiconductor circuits arranged in said semiconductor substrate.

11. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in a part of a surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region and connected to an input pad for receiving an external signal,

second semiconductor regions of the first conductivity type respectively formed at opposing sides of the first semiconductor region in the surface region of said well region, said second semiconductor regions being connected to a ground potential; and

a third semiconductor region of the second conductivity type formed entirely within the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions, and said third semiconductor region being connected to the ground potential through a resistor,

wherein said well region includes no semiconductor region other than said first, second, and third semiconductor regions and is formed independently of other semiconductor circuit arranged in said semiconductor substrate.

12. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in a part of a surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region and connected to an input pad for receiving an external signal;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of the first semiconductor region in the surface region of said well region, said second semiconductor regions being connected to a ground potential;

a third semiconductor region of the second conductivity type formed entirely within the surface region of said well region and connected to the ground potential, said third semiconductor region being arranged around said second semiconductor regions; and

a resistor connected to said third semiconductor region,

wherein said first semiconductor region, said well region, and said second semiconductor regions form a parasitic bipolar transistor between said input pad and the ground potential, and said first semiconductor region, said well region, and said third semiconductor region form a parasitic diode in parallel with said parasitic bipolar transistor between said input pad and the ground potential, and

wherein said well region includes no semiconductor region other than said first, second, and third semiconductor regions and is formed independently of other semiconductor circuits arranged in said semiconductor substrate.

13. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in a part of a surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region, said first semiconductor region being connected to an input pad for receiving an external signal;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in the surface region of said well region;

a third semiconductor region of the second conductivity type formed in the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions; and

a fourth semiconductor region of the first conductivity type formed in said well region immediately below said first semiconductor region, an impurity concentration of said fourth semiconductor region being lower than an impurity concentration of said first semiconductor region,

wherein said well region includes no semiconductor region other than said first, second, third, and fourth semiconductor region and is formed independently of other semiconductor circuits arranged in said semiconductor substrate, said second semiconductor regions are connected to a first potential, and said third semiconductor region is connected to a second potential lower than the first potential,

wherein said first semiconductor region, said well region, and said second semiconductor regions form a parasitic bipolar transistor between said input pad and the first potential, and said first semiconductor region, said well region, and said third semiconductor region form a parasitic diode between said input pad and the second potential, and

wherein the first potential is a ground potential and the second potential is a back gate bias potential.