Integrated circuit (IC) with a two-terminal diode device to protect metal-oxide-metal capacitors from ESD damage

• US 5,594,266 A
• Filed: 10/20/1995
• Issued: 01/14/1997
• Est. Priority Date: 02/18/1994
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Krieger, William A., Beigel, David F., Feindt, Susan L.
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US08/546,188
• Time in Patent Office: 452 Days
• Field of Search: 257/355, 257/367, 257/481, 257/546, 257/551, 257/603, 257/605, 257/606
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.

Claims

1. An integrated-circuit (IC) chip comprising circuitry with transistors and capacitors, said circuitry being connected by a lead to an external terminal point of said IC chip, said IC chip further being formed with a clamp device to prevent damage to any capacitor element of said circuitry from electrostatic discharge (ESD) striking said terminal point, said clamp device comprising a diode with first and second electrodes and being formed during the process of forming the chip including:

isolation means defining a clamp device region within which said clamp device is formed;

said clamp device region including a silicon region with dopant of one type;

said silicon region including a first plug with dopant of said one type and extending at least part way along the outer reaches of said silicon region to serve as a low resistance current path for one electrode of the diode;

first contact means to establish a first contact to make electrical connection to said first plug;

said silicon region further including a second plug laterally interiorly of and separate from said first plug, said second plug being diffused throughout with dopant of type opposite said one type to serve the function of the other electrode of the diode;

said second plug with said diffusion of opposite-type dopant being free of dopant of said one type so as to provide homogeneity of dopant type throughout said second plug;

second contact means to establish a second contact to make electrical connection to said second plug;

means connecting one of said contacts to a line of fixed potential; and

means connecting the other of said contacts to said lead between said terminal point and said IC circuitry so as to intercept and shunt to said line of fixed potential electrostatic pulse energy received from said terminal point thereby to provide for dissipation of the ESD energy to prevent it from damaging said IC circuitry.

2. An IC chip as claimed in claim 1, wherein said clamp device region comprises a buried layer region of silicon heavily doped with said one type of dopant and an epitaxial layer over said buried layer region lightly doped with said one type of dopant;

said second plug being formed to extend from the upper surface of said clamp device region down to said buried layer region.

3. An IC chip as claimed in claim 2, wherein the dopant densities of said buried layer region and the diffused region comprising said other electrode of the diode are sufficiently high to achieve subsurface avalanche breakdown.

4. An IC chip as claimed in claim 2, wherein said first and second plugs are formed in said epitaxial layer above said buried layer region.