J-leaded semiconductor package having a plurality of stacked ball grid array packages

• US 5,594,275 A
• Filed: 11/18/1994
• Issued: 01/14/1997
• Est. Priority Date: 11/18/1993
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Young S., Ahn, Seung H.
• Primary Examiner(s): WHITEHEAD JR, CARL W
• Application Number:
  US08/345,385
• Time in Patent Office: 788 Days
• Field of Search: 257/679, 257/686, 257/690, 257/697, 257/698, 257/701, 257/702, 257/737, 257/738, 257/762, 257/774, 257/777, 257/798, 257/696, 257/685
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/02 Containers; Seals H01L23/12, H01L23/34, H01L23/48, H01L23/552, H01L23/66 take precedence; for memories G11C
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device having at least one semiconductor chip loaded on a lower surface of a printed circuit board, electrode terminals of the semiconductor chip wire-bonded to terminals on the printed circuit board, and a connection portion of the semiconductor chip and wires encapsulated by means of encapsulating resin includes a semiconductor device of three-dimensional structure having the printed circuit board reversely mounted, the terminals of the printed circuit board connected to external terminals via through holes, and at least one semiconductor device stacked on an upper surface of the printed circuit board, thereby interconnecting respective semiconductor devices while interposing solder balls to be mounted to other printed circuit boards by leads being the external terminals. Thus, a ball grid array (BGA) package able to be stacked inside a small out-line J-lead (SOJ) package is used for performing interconnection to make the BGA overcome a typically two-dimensional flat mounting and attain a three-dimensional surface mounting structure while being perfectly compatible with a currently-available mounting process on the main substrate, thereby improving mounting efficiency.

Claims

1. A semiconductor device comprising a stacked plurality of ball grid array (BGA) packages, each said BGA package comprising:

a circuit board having;

a lower surface and an upper surface,

a plurality of connection leads provided on said lower surface,

a plurality of first and second land patterns electrically connected to respective said connection leads, and

a plurality of solder ball pads provided on said upper surface and electrically connected to said first land patterns;

a semiconductor chip mounted on said lower surface of said circuit board;

a encapsulation resin portion covering at least said semiconductor chip; and

a plurality of solder balls formed on said solder ball pads,

wherein said plurality of BGA packages are stacked and interconnected by connecting said plurality of solder balls of a first said BGA package to respective said first land patterns of a second said BGA package, and

wherein one of said stacked BGA packages has external leads electrically connected to respective said first and second land patterns.

2. A semiconductor device as claimed in claim 1, wherein said circuit board is formed by thermostable bismaleimidetriazine (BT) resin and thermostable epoxy, and is plated with gold (Au) to a thickness of approximately 0.5 μ

m.

3. A semiconductor device as claimed in claim 1, wherein said first land patterns are disc-shaped.

4. A semiconductor device as claimed in claim 1, wherein the upper and lower surfaces of said circuit board are electrically interconnected to each other by way of said through holes.

5. A semiconductor device as claimed in claim 1, wherein said circuit board is further provided with interlayer connection terminals on said lower surface of said circuit board and are electrically connected to said through holes, wherein a conductive portion and a through hole portion except the portions connected by said solder balls are coated with solder resist.

6. A semiconductor device as claimed in claim 1, wherein one of said BGA packages is provided with external leads plated with a copper-based material.

7. A semiconductor device as claimed in claim 6, wherein said plurality of solder balls and said external leads are formed on opposite sides of said circuit board.

8. A semiconductor device as claimed in claim 6, wherein said external leads are bent in a shape of "J".

9. A semiconductor device as claimed in claim 1, wherein said semiconductor chip is electrically connected to said plurality of connection leads by corresponding wires.

10. A semiconductor device as claimed in claim 9, wherein said encapsulation resin covers said semiconductor chip and said corresponding wires.