Low power combinational logic circuit

• US 5,594,368 A
• Filed: 04/19/1995
• Issued: 01/14/1997
• Est. Priority Date: 04/19/1995
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Usami, Kimiyoshi
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US08/423,943
• Time in Patent Office: 636 Days
• Field of Search: 326/80, 326/81, 326/63, 326/68
• US Class Current: 326/80
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption

Abstract

The power consumption by a combinational logic circuit having primary input and output terminals is reduced. The constituent gates of the combinational logic are clustered in terms of the operating voltage levels thereof. First, the gates driven with the highest operating voltage are clustered just adjacent to the primary input terminals. Next, the gates driven with the next higher voltage are clustered adjacent to the primary input terminals only through the gates driven with the highest voltage, followed by repetition of the same clustering procedure in the order of the operating voltage level. Finally, the gates driven with the lowest operating voltage are clustered Just adjacent to the primary output terminals.

Claims

1. A combinational logic circuit having at least one primary input terminal and at least one primary output terminal, comprising:

a plurality of first gates each of which has input and output nodes and is driven with a first operating voltage; and

a plurality of second gates each of which has input an output nodes and is driven with a second operating voltage which is lower than said first operating voltage,

wherein any one of the output nodes of said second gates is connected only to either one of the input nodes of said second gates or one of said primary output terminals but not to any one of the input nodes of said first gates, and

wherein a level converter circuit is provided between at least one of said primary output terminals and at least one of said second gates.

2. The combinational logic circuit as claimed in claim 1 wherein said level converter circuit is a level convertible latch circuit which can hold a signal input thereto and convert a voltage level of the input signal from said second operating voltage to said first operating voltage.

3. The combinational logic circuit as claimed in claim 2 wherein said level convertible latch circuit is composed of a latch circuit comprising a pair of inverters driven with said first operating voltage and coupled to each other with the input node of each inverter connected to the output node of the other, the input node of one of said inverters being connected to ground through a first transistor which is turned on and off in response to the signal at said at least one of said second gates, the input node of the other of said-inverters being connected to ground through a second transistor which is turned on and off in response to the signal at said at least one of said second gates in an opposite manner to operation of said first transistor.

4. A combinational logic circuit having at least one primary input terminal and at least one primary output terminal, comprising:

a plurality of first gates each of which has input and output nodes and is driven with a first operating voltage;

a plurality of second gates each of which has input and output nodes and is driven with a second operating voltage which is lower than said first operating voltage; and

a plurality of third gates each of which has input and output nodes and is driven with a third operating voltage which is lower than said first operating voltage and higher than said second operating voltage,

wherein any one of the output nodes of said second gates is connected only to either one of the input nodes of said second gates or one of said primary output terminals but not to any one of the input nodes of said first gates, and

wherein the input node of any one of said third gates is connected only to either one of the output nodes of said first gates or one of said primary input terminals but not to any one of the input nodes of said first gates.