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Integrated circuit input/output ESD protection circuit with gate voltage regulation and parasitic zener and junction diode

  • US 5,594,611 A
  • Filed: 01/12/1994
  • Issued: 01/14/1997
  • Est. Priority Date: 01/12/1994
  • Status: Expired due to Term
First Claim
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1. An electro-static discharge protection circuit adapted for use in an integrated circuit, comprising:

  • a first protective field effect transistor connected between a pad of said integrated circuit and a potential of said integrated circuit and having a gate, said first transistor responsive to a voltage applied to said gate to control a current through said first transistor; and

    a voltage regulator connected between said gate of said first protective transistor and said potential of said IC, said voltage regulator operative to apply said voltage to said gate such that a desired amount of current flows through said first transistor when an electro-static discharge is applied to said pad, wherein;

    said potential is a ground potential and said first protective transistor is an NMOS field effect transistor having a drain electrically connected to said pad, and a source electrically connected to said ground potential; and

    said voltage regulator comprises;

    a first diode having an anode connected to said gate of said first transistor, and a cathode;

    a second diode having an anode connected to said cathode of said first diode, and a cathode; and

    a third diode having an anode connected to said cathode of said second and a cathode connected to said ground potential of said IC.

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