Integrated circuit input/output ESD protection circuit with gate voltage regulation and parasitic zener and junction diode
First Claim
1. An electro-static discharge protection circuit adapted for use in an integrated circuit, comprising:
- a first protective field effect transistor connected between a pad of said integrated circuit and a potential of said integrated circuit and having a gate, said first transistor responsive to a voltage applied to said gate to control a current through said first transistor; and
a voltage regulator connected between said gate of said first protective transistor and said potential of said IC, said voltage regulator operative to apply said voltage to said gate such that a desired amount of current flows through said first transistor when an electro-static discharge is applied to said pad, wherein;
said potential is a ground potential and said first protective transistor is an NMOS field effect transistor having a drain electrically connected to said pad, and a source electrically connected to said ground potential; and
said voltage regulator comprises;
a first diode having an anode connected to said gate of said first transistor, and a cathode;
a second diode having an anode connected to said cathode of said first diode, and a cathode; and
a third diode having an anode connected to said cathode of said second and a cathode connected to said ground potential of said IC.
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Accused Products
Abstract
An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.
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Citations
10 Claims
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1. An electro-static discharge protection circuit adapted for use in an integrated circuit, comprising:
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a first protective field effect transistor connected between a pad of said integrated circuit and a potential of said integrated circuit and having a gate, said first transistor responsive to a voltage applied to said gate to control a current through said first transistor; and a voltage regulator connected between said gate of said first protective transistor and said potential of said IC, said voltage regulator operative to apply said voltage to said gate such that a desired amount of current flows through said first transistor when an electro-static discharge is applied to said pad, wherein; said potential is a ground potential and said first protective transistor is an NMOS field effect transistor having a drain electrically connected to said pad, and a source electrically connected to said ground potential; and said voltage regulator comprises; a first diode having an anode connected to said gate of said first transistor, and a cathode; a second diode having an anode connected to said cathode of said first diode, and a cathode; and a third diode having an anode connected to said cathode of said second and a cathode connected to said ground potential of said IC. - View Dependent Claims (2, 3, 4, 5)
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6. An electro-static discharge protection circuit adapted for use in an integrated circuit, comprising:
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a first protective field effect transistor connected between a pad of said integrated circuit and a potential of said integrated circuit and having a gate, said first transistor responsive to a voltage applied to said gate to control a current through said first transistor; and a voltage regulator connected between said gate of said first protective transistor and said potential of said IC, said voltage regulator operative to apply said voltage to said gate such that a desired amount of current flows through said first transistor when an electro-static discharge is applied to said pad; wherein said potential is a ground potential and said first protective transistor is an NMOS field effect transistor having a drain electrically connected to said pad, and a source electrically connected to said ground potential; and the circuit further comprises a second protective field effect transistor having a gate electrically connected to said pad and said drain of said first protective transistor, a drain connected to said gate of said first transistor, a drain connected to said gate of said first transistor, and a source connected to said ground potential of said IC. - View Dependent Claims (7)
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8. An electro-static discharge protection circuit adapted for use in an integrated circuit, comprising:
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a first protective field effect transistor connected between a pad of said integrated circuit and a potential of said integrated circuit and having a gate, said first transistor responsive to a voltage applied to said gate to control a current through said first transistor; and a voltage regulator connected between said gate of said first protective transistor and said potential of said IC, said voltage regulator operative to apply said voltage to said gate such that a desired amount of current flows through said first transistor when an electro-static discharge is applied to said pad; wherein said IC further includes a first operative transistor and a second operative transistor, wherein said first operative transistor is a PMOS FET and said second operative transistor is an NMOS FET, a drain of said first operative transistor electrically connected to a drain of said second operative transistor and to said pad, a source of said first operative transistor electrically connected to a supply voltage of said IC, and a source of said second operative transistor electrically connected to a ground potential of said IC, such that said first operative transistor forms a parasitic conductive path between said pad and said ground potential. - View Dependent Claims (9, 10)
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Specification