System for synthesizing field programmable gate array implementations from high level circuit descriptions

• US 5,594,657 A
• Filed: 06/07/1995
• Issued: 01/14/1997
• Est. Priority Date: 09/27/1993
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Woo, Nam-Sung, Cantone, Michael R.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/473,620
• Time in Patent Office: 587 Days
• Field of Search: 364/488-491, 364/578
• US Class Current: 716/104
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing

Abstract

A system is disclosed for synthesizing field programmable gate array (FPGA) implementations from high level circuit descriptions. A designer may describe circuits using a textual language or a graphics tool. The system will compile such circuit descriptions into technology mapped descriptions for use with FPGA'"'"'s.

The system will support both random logic circuits and data path circuits. The system uses advanced optimization techniques to produce efficient FPGA implementations. Thus, the system produces high quality results while providing users with a high level of abstraction in design, and thus frees the user from architectural details of the target FPGA.

Claims

1. A structured circuit synthesis system for optimizing a circuit implementation in a field programmable gate array, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the system comprising:

a computer processor;

means for storing a description of a first electronic circuit design module specifying an output signal and a polarity of said output signal, and a second electronic circuit design module specifying an input signal and a polarity of said input signal, said output signal of the first module corresponding to the input signal of said second module; and

means for receiving the input signal and the output signal and reversing the signal polarities of said input signal and said output signal to synthesize multiple modules simultaneously to reduce the number of programmable logic cells required to implement said first module and said second module in the field programmable gate array.

2. The system of claim 1 wherein said description of electronic design modules is a textual language in terms of parameterized modules.

3. The system of claim 1 wherein said description of electronic circuit design modules is a collection of graphical icons representative of electronic design elements and attributes of said modules associated with said icons.

4. The system of claim 1, further comprising means for producing output for processing by a placement tool.

5. The system of claim 1, wherein the means for receiving comprises means for receiving descriptions of at least one of finite state machines and Boolean equations.

6. A structured circuit synthesis system for synthesizing a circuit implementation in a field programmable gate array, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the system comprising:

a computer processor;

means for storing a textual description of a first electronic circuit design element connected to a second electronic circuit design element, wherein the circuit design elements comprise at least a random logic circuit and a datapath module;

means for receiving the textual description and implementing said first electronic circuit design element and said second electronic circuit design element in at least one programmable logic cell such that the output of said first electronic circuit design element is connected to said second electronic circuit design element; and

means for optimizing the field programmable gate array implementation of said first and second electronic circuit design elements.

7. The system of claim 6 wherein said means for optimizing comprises:

means for implementing said first and second electronic circuit design elements in at least one programmable logic cell so as to minimize the number of programmable logic cells.

8. The system of claim 6 wherein said means for optimizing comprises:

means for implementing said first and second electronic circuit design elements in at least one programmable logic cell so as to minimize the timing of said implementation.

9. The system of claim 6 wherein said means for optimizing comprises:

means for implementing said first electronic circuit design element and said second electronic circuit design element in one programmable logic cell.

10. A method for optimizing a field programmable gate array configuration with a structured circuit synthesis system, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the method comprising the steps of:

storing a description of a first electronic circuit design module specifying an output signal and a polarity of said output signal, and a second electronic circuit design module specifying an input signal and a polarity of said input signal, said output signal of the first module corresponding to the input signal of said second module; and

receiving the input signal and the output signal and reversing the signal polarities of said input signal and said output signal to synthesize multiple modules simultaneously to reduce the number of programmable logic cells required to implement said first module and said second module in the field programmable gate array.

11. The method of claim 10 wherein said description of electronic circuit design modules is a textual language in terms of parameterized modules.

12. The method of claim 10 wherein said description of electronic circuit design modules is a collection of graphical icons representative of said electronic circuit design modules and attributes of said modules associated with said icons.

13. A method for synthesizing a circuit implementation in a field programmable gate array with a structured circuit synthesis system, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the method comprising the steps of:

storing a textual description of a first electronic circuit design element connected to a second electronic circuit design element, wherein the circuit design elements comprise at least a random logic circuit and a datapath module;

receiving the textual description and implementing said first electronic circuit design element and said second electronic circuit design element in at least one programmable logic cell such that the output of said first electronic circuit design element is connected to said second electronic circuit design element; and

optimizing the field programmable gate array implementation of said first and second electronic circuit design elements.

14. The method of claim 13 wherein said step of optimizing further comprises the step of:

implementing said first and second electronic circuit design elements in at least one programmable logic cell so as to minimize the number of programmable logic cells.

15. The method of claim 13 wherein said step of optimizing further comprises the step of:

implementing said first and second electronic circuit design elements in at least one programmable logic cell so as to minimize the timing of said implementation.

16. The method of claim 13 wherein said step of optimizing further comprises the step of:

implementing said first electronic circuit design element and said second electronic circuit design element in one programmable logic cell.

17. A system for synthesizing circuits in a field programmable gate array from a high level description, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the system comprising:

means for providing an electronic circuit description describing a plurality of electronic circuit elements in terms of parameterized modules, said electronic circuit elements including finite state machines;

a compiler for compiling said electronic circuit description into field programmable gate array configuration data;

means for producing a field programmable gate array implementation from said field programmable gate array configuration data; and

means for optimizing the field programmable gate array implementation.

18. The system of claim 17 wherein said means for providing an electronic circuit description further comprises:

a graphical display monitor for displaying a plurality of icons representative of said plurality of electronic circuit elements in a first portion of said graphical display monitor;

a graphical input device for choosing electronic circuit elements by positioning said icons in a second portion of said graphical display monitor;

an input device for assigning attributes to chosen electronic circuit elements; and

a translator for generating said electronic circuit description from said chosen electronic circuit elements and assigned attributes.

19. The system of claim 17 wherein said field programmable gate array configuration data is a field programmable gate array application netlist.

20. The system of claim 17 wherein said electronic circuit description describes a memory module containing initial contents.

21. A system for synthesizing circuits in a field programmable gate array from a high level description, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the system comprising:

means for providing an electronic circuit description describing a plurality of electronic circuit elements in terms of parameterized modules;

a compiler for compiling said electronic circuit description into field programmable gate array configuration data including group information identifying a plurality of programmable logic cells as belonging to a group;

means responsive to said group information for receiving said programmable gate array configuration data and for generating a field programmable gate array implementation wherein said plurality of programmable logic cells identified as belonging to a group are located closer to each other than to programmable logic cells not identified as belonging to the group; and

means for optimizing the field programmable gate array implementation.

22. The system of claim 21 wherein said electronic circuit elements include finite state machines.

23. The system of claim 21 wherein said means responsive to said group information includes a placement tool.

24. A method for synthesizing circuits in a field programmable gate array from a high level description, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the method comprising the steps of:

providing an electronic circuit description describing a plurality of electronic circuit elements in terms of parameterized modules, said electronic circuit elements including finite state machines;

compiling said electronic circuit description into field programmable gate array configuration data;

producing a field programmable gate array implementation from said field programmable gate array configuration data; and

optimizing the field programmable gate array implementation.

25. The method of claim 24 wherein said step of providing an electronic circuit description further comprises the steps of:

displaying a plurality of icons representative of said plurality of electronic circuit elements in a first portion of a graphical display monitor;

choosing electronic circuit elements by positioning said icons in a second portion of said graphical display monitor using a graphical input device;

assigning attributes to chosen electronic circuit elements; and

generating said electronic circuit description from said chosen electronic circuit elements and assigned attributes.

26. The method of claim 24 wherein said field programmable gate array configuration data is a field programmable gate array application netlist.

27. The method of claim 24 wherein said electronic circuit description describes a memory module containing initial contents.

28. A method for synthesizing circuits in a field programmable gate array from a high level description, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the method comprising the steps of:

providing an electronic circuit description describing a plurality of electronic circuit elements in terms of parameterized modules;

compiling said electronic circuit description into field programmable gate array configuration data including group information identifying a plurality of programmable logic cells as belonging to a group;

generating a field programmable gate array implementation from said gate array configuration data, wherein said plurality of programmable logic cells identified as belonging to a group are located closer to each other than to programmable logic cells not identified as belonging to the group; and

optimizing the field programmable gate array implementation.

29. The method of claim 28 wherein said electronic circuit elements include finite state machines.