Method for programming a single EPROM or flash memory cell to store multiple bits of data that utilizes a punchthrough current

• US 5,594,685 A
• Filed: 04/13/1995
• Issued: 01/14/1997
• Est. Priority Date: 12/16/1994
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Chi, Min-hwa, Bergemont, Albert
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/422,146
• Time in Patent Office: 642 Days
• Field of Search: 365/185.03, 365/185.27, 365/185.18, 365/168, 365/185.28, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 2211/5625 Self-converging multilevel programming

Abstract

Multiple bits of data can be programmed into a single EPROM or FLASH memory cell by applying one of a number of programming voltages to the control gate of a memory cell that forms a punchthrough current during programming. The punchthrough current forms substrate hot electrons which, in addition to the channel hot electrons, accumulate on the floating gate. The charge on the floating gate converges to a stable threshold value which is linearly related to the programming voltage utilized. In addition, by utilizing the substrate hot electrons, a much lower control gate voltage can be utilized during programming.

Claims

1. A method for programming a single floating-gate memory cell to have one of three or more threshold voltages, the memory cell having a source and drain formed a distance apart in the well that define a channel therebetween, a layer of first insulation material formed over the channel, a floating gate formed over the layer of first insulation material, a layer of second insulation material formed over the floating gate, and a control gate formed over the layer of second insulation material, the method comprising the steps of:

selecting one of three or more programming voltages as a selected programming voltage, the three or more programming voltages corresponding to said three or more threshold voltages;

applying a first voltage to the well;

applying the first voltage to the source so that the source-to-well junction is in equilibrium;

applying a second voltage to the drain so that the drain-to-well junction is reverse-biased, the drain-to-source voltage is positive, and a punchthrough current is induced to flow from the drain to the source; and

applying the selected programming voltage to the control gate of the memory cell.

2. The method of claim 1 wherein the first voltage includes ground.

3. The method of claim 1 wherein the second voltage is greater than the first voltage by two or more volts.

4. The method of claim 1 wherein a maximum programming voltage is less than or equal to five volts.

5. A method for programming a single floating-gate memory cell to have one of three or more threshold voltages, the memory cell having a source and drain formed a distance apart in the well that define a channel therebetween, a layer of first insulation material formed over the channel, a floating gate formed over the layer of first insulation material, a layer of second insulation material formed over the floating gate, and a control gate formed over the layer of second insulation material, the method comprising the steps of:

providing the floating-gate memory cell so that a punchthrough current flows from the drain to source during programming;

selecting one of three or more programming voltages as a selected programming voltage, the three or more programming voltages corresponding to said three or more threshold voltages;

applying a first voltage to the well;

applying the first voltage to the source so that a source-to-well junction is in equilibrium;

.

applying a second voltage to the drain so that a drain-to-well junction is reverse-biased, the second voltage being greater than the first voltage; and

applying the selected programming voltage to the control gate of the memory cell for a time less than or equal to 50 milliseconds.

6. A method for programming a single floating-gate memory cell to have one of three or more threshold voltages, the memory cell having a source and drain formed a distance apart in the well that define a channel therebetween, a layer of first insulation material formed over the channel, a floating gate formed over the layer of first insulation material, a layer of second insulation material formed over the floating gate, and a control gate formed over the layer of second insulation material, the method comprising the steps of:

selecting one of three or more programming voltages as a selected programming voltage, the three or more programming voltages corresponding to said three or more threshold voltages; and

applying the selected programming voltage to the control gate, a first voltage to the source and well, and a second voltage to the drain so that the drain-to-well junction is reverse-biased, the drain-to-source voltage is positive, and a punchthrough current is induced to flow from the drain to the source.