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Programmable architecture and methods for motion estimation

  • US 5,594,813 A
  • Filed: 02/19/1992
  • Issued: 01/14/1997
  • Est. Priority Date: 02/19/1992
  • Status: Expired due to Term
First Claim
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1. An apparatus for performing a variety of operations relating to motion estimation, including pixel differences, sum of absolute pixel differences, and pixel averaging, comprising:

  • a first memory having a plurality of addressable locations N pixels in width, a first write port, and first and second read ports, wherein N pixels from any one of said addressable locations are accessible in parallel on each of said first and second read ports during an address cycle;

    a second memory having a plurality of addressable locations N pixels in width, a second write port, and third and fourth read ports, wherein N pixels from any one of said addressable locations and N pixels from an adjacent addressable location are accessible in parallel on each of said third and fourth read ports during an address cycle;

    a first shifter having an input port coupled to said third read port and an output port N pixels in width;

    a second shifter having an input port coupled to said fourth read port and an output port N pixels in width;

    a first multiplexer having one input port coupled to said first and second read ports, another input port coupled to the output port of said first shifter, and an output port;

    a second multiplexer having one input port coupled to the output ports of said first and second shifters, another input port coupled to the output port of said second shifter, and an output port;

    an arithmetic unit having a first operand input port coupled to the output port of said first multiplexer for receiving a first operandi, a second operand input port coupled to the output port of said second multiplexer for receiving a second operandi, a first output port for furnishing the absolute value of a difference between said first and second operandi, and a second output port for selectively furnishing one of a difference between said first and second operandi, and an average of said first and second operandi; and

    an adder coupled to the first output port of said arithmetic unit;

    wherein the second output port of said arithmetic unit is routed to said first and second write ports.

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