Graphics subsystem with coarse subpixel correction

• US 5,594,854 A
• Filed: 03/24/1995
• Issued: 01/14/1997
• Est. Priority Date: 03/24/1995
• Status: Expired due to Term

• Current Assignee: ZiiLabs Inc., Ltd. (Creative Technology Ltd.)
• Original Assignee: 3DLabs Incorporated Limited (Creative Technology Ltd.)
• Inventors: Baldwin, David R., Bigos, Andrew
• Primary Examiner(s): Jankus, Almis R.
• Application Number:
  US08/410,220
• Time in Patent Office: 662 Days
• Field of Search: 395/120, 395/126, 395/133-136, 395/141, 395/142, 395/162-166, 395/800
• US Class Current: 345/441
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering

Abstract

A graphics processing system in which sub-pixel correction is implemented in a new and more economical way. A half-pixel offset is originally imposed on both the X and Y axes, so the sub-pixel correction value may be positive or negative. A relatively coarse resolution is used for subpixel correction, so that the DDAs (and other functional blocks) do not have to perform a full multiply: instead they merely perform simple add operations (addition of partial products) to derive the necessary offset from the delta-X values, using a proportionality constant provided by the rasterizer. The DDAs preferably include a "guard band" in their calculations, so that values which exceed the maximum (e.g. 255, for 8 bits of subpixel resolution) do not wrap to zero; instead the output is held at the maximum until the computed value comes down below the maximum.

Claims

1. A graphics system comprising:

a rasterizer which generates a sequence of pixel location identifiers and associated operation specifiers;

one or more digital differential analyzer units (DDA units) connected to receive said sequence of pixel location identifiers and associated operation specifiers from said rasterizer;

wherein ones of said operation specifiers generated by said rasterizer include commands for programming said DDA units to perform incremental changes in pixel attributes;

and wherein ones of said operation specifiers generated by said rasterizer include at least one delta value for incrementing, and also include a subpixel offset values which indicate a value proportional to said delta value;

and wherein said DDA units generate said incremental changes in pixel attributes, from said delta value and said subpixel offset value, using calculations which use multiplexing operations but do not use any multiply operations.

2. The graphics processing subsystem of claim 1, wherein said delta value includes not only a first incrementation value for incrementing in the direction of a scanline, but also a second incrementation value for incrementing along the leading edge of the primitive being rendered.

3. The graphics processing subsystem of claim 2, wherein said second incrementation value contains at least two non-zero scalar components.

4. The graphics processing subsystem of claim 1, wherein said rasterizer and all of said DDA units are integrated into a single integrated circuit.

5. The graphics processing subsystem of claim 1, wherein said rasterizer and said DDA units are interconnected in a pipeline architecture.

6. The graphics processing subsystem of claim 1, wherein said DDA units include multiple color DDA units and at least one other DDA unit.

7. The graphics processing subsystem of claim 1, wherein said DDA units include at least one color DDA unit and a depth DDA unit.

8. A graphics system comprising:

a rasterizer which generates a sequence of pixel location identifiers and associated operation specifiers;

one or more digital differential analyzer units (DDA units) connected to receive said sequence of pixel location identifiers and associated operation specifiers from said rasterizer;

wherein ones of said operation specifiers generated by said rasterizer include commands for programming said DDA units to perform incremental changes in pixel attributes;

and wherein ones of said operation specifiers generated by said rasterizer also include subpixel offset values, and wherein said DDA units use said subpixel offset values in calculating pixel attributes, but do not use said subpixel offset values as inputs to any multiply;

and wherein said subpixel offset values have a resolution between one and six bits, inclusive.

9. The graphics processing subsystem of claim 8, wherein said rasterizer and all of said DDA units are integrated into a single integrated circuit.

10. The graphics processing subsystem of claim 8, wherein said rasterizer and said DDA units are interconnected in a pipeline architecture.

11. The graphics processing subsystem of claim 8, wherein said DDA units include multiple color DDA units and at least one other DDA unit.

12. The graphics processing subsystem of claim 8, wherein said DDA units include at least one color DDA unit and a depth DDA unit.

13. A graphics system comprising:

a rasterizer which generates a sequence of pixel location identifiers and associated operation specifiers;

one or more digital differential analyzer units (DDA units) connected to receive said sequence of pixel location identifiers and associated operation specifiers from said rasterizer;

wherein ones of said operation specifiers generated by said rasterizer include commands for programming said DDA units to perform incremental changes in pixel attributes;

and wherein ones of said operation specifiers generated by said rasterizer also include subpixel offset values, and wherein said DDA units use said subpixel offset values in calculating pixel attributes, but do not use said subpixel offset values as inputs to any floating-point multiply;

and wherein said DDA units calculate subpixel offset values with an internal resolution which includes a range of more than one pixel width, and with a guard band such that calculated subpixel offsets which exceed the width of a pixel do not wrap to zero, but are clamped at a maximum value until the computed value comes down below the maximum.

14. The graphics processing subsystem of claim 13, wherein said rasterizer and all of said DDA units are integrated into a single integrated circuit.

15. The graphics processing subsystem of claim 13, wherein said rasterizer and said DDA units are interconnected in a pipeline architecture.

16. The graphics processing subsystem of claim 13, wherein said DDA units include multiple color DDA units and at least one other DDA unit.

17. The graphics processing subsystem of claim 13, wherein said DDA units include at least one color DDA unit and a depth DDA unit.

18. A rasterizer which generates a sequence of pixel location identifiers and associated operation specifiers, comprising:

means for generating operation specifiers which include commands for programming one or more downstream DDA units to perform incremental changes in pixel attributes;

wherein ones of said operation specifiers generated by said rasterizer also include subpixel offset values specified as multiplexer inputs;

means for outputting said operation specifiers for rendering by units which include one or more DDA units.

19. A method for rendering, comprising the steps of:

generating a sequence of pixel location identifiers and associated operation specifiers, in a rasterizer;

wherein ones of said operation specifiers include commands for incremental changes in pixel attributes; and

wherein ones of said operation specifiers generated by said rasterizer also include subpixel offset values;

receiving said sequence of pixel location identifiers and associated operation specifiers in one or more digital differential analyzer units (DDA units); and

using said subpixel offset values, said DDA units, for calculating pixel attributes, but not as inputs to any multiply operation;

and wherein said DDA units calculate subpixel offset values with an internal resolution which includes a range of more than one pixel width, and with a guard band such that calculated subpixel offsets which exceed the width of a pixel do not wrap to zero, but are clamped at a maximum value until the computed value comes down below the maximum.

20. A digital differential analyzer unit (DDA unit), comprising:

an input connection for receiving sequences of operation specifiers from a rasterizer, individual ones of said operation specifiers including commands for programming said DDA units to generate a series of pixel outputs, in which at least one parameter is incrementally changed over a respective sequence of pixels;

internal calculation logic configured to calculate said parameter for each pixel in said respective sequence of pixels, with N bits of resolution; and

an output connection connected to output said parameter for each pixel in said respective sequence of pixels, as a digital value with M bits of resolution, wherein M is less than N;

wherein said internal calculation logic includes one or more most-significant-bits which are not included in said N bits;

whereby, when said internal calculation logic obtains a parameter value which would overflow said M bits of output, said internal calculation logic outputs a M-bit clamped value.

21. The DDA unit of claim 20, wherein M is less than N-1.

22. The DDA unit of claim 20, wherein M is less than N-3.

23. The DDA unit of claim 20, wherein said parameter is a color value.

24. The DDA unit of claim 20, wherein said parameter is a depth value.

25. The DDA unit of claim 20, wherein said DDA unit is included within a single block of a pipelined multiprocessor architecture.