Emulation system for emulating CPU core, CPU core with provision for emulation and ASIC having the CPU core

• US 5,594,890 A
• Filed: 02/23/1994
• Issued: 01/14/1997
• Est. Priority Date: 02/25/1993
• Status: Expired due to Term

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Hara, Kazuhiko, Katayama, Takao, Yoshioka, Keiichi, Yamaura, Shinichi
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): NGUYEN, TAN QUANG
• Application Number:
  US08/200,705
• Time in Patent Office: 1,056 Days
• Field of Search: 395/500, 395/200.12, 364/578, 364/579, 371/11.1, 371/16.2, 371/22.2, 371/22.6, 371/22.5
• US Class Current: 703/23
• CPC Class Codes: G06F 11/3652 in-circuit-emulation [ICE] arrangements

Abstract

An IC is provided with a CPU core selected from a plurality of CPU cores, each of which has a specific function. Each CPU core has a system-bus terminal and a common emulator connecting-exclusive terminal. The IC is also provided with a predetermined function device connected to a system bus of the selected CPU core. An emulation bus connects an emulator to the selected CPU core via the common emulator connecting-exclusive terminal. An emulator performs emulation on the selected CPU core which is connected via the emulation bus when the selected CPU core is in a monitor mode. The number of terminal elements and the function associated with each terminal element of the common emulator connecting-exclusive terminal are identical among the common emulator connecting-exclusive terminals.

Claims

1. An emulation system comprising:

an integrated circuit (IC) provided with a central processing unit (CPU) core arbitrarily selected from a plurality of CPU cores, each of said CPU cores having system-bus terminals, a system bus and a plurality of common emulator connecting-exclusive terminals, said IC being also connected to a predetermined device via said system bus associated with the selected CPU core;

an emulation bus connectable to said common emulator connecting-exclusive terminals of said selected CPU core; and

an emulator for performing emulation of said selected CPU core connected to said emulation bus when said selected CPU core is selectively in a monitor mode.

2. An emulation system according to claim 1, wherein

a number of said common emulator connecting-exclusive terminals and a corresponding function associated with each of said common emulator connecting-exclusive terminals are identical among said plurality of said CPU cores.

3. The emulation system according to claim 2, wherein said selected CPU core further comprises an emulation-bus use permission input terminal in addition to the common emulator connecting-exclusive terminals, said emulation-bus use permission input terminal being used for supplying therethrough a signal controlling whether or not said selected CPU core operates in the monitor mode via the common emulator connecting-exclusive terminal.

4. The emulation system according to claim 2, wherein said selected CPU core is provided with at least one monitor-mode setting signal input terminal for supplying therethrough a signal which sets one of a plurality of bus-control modes for controlling whether the system-bus terminal or the common emulator connecting-exclusive terminal provided on the selected CPU core is selected to be given a bus control right concerning said selected CPU core.

5. The emulation system according to claim 4, wherein said plurality of bus-control modes comprises:

a normal mode wherein said emulator breaks, resets, and forcibly inserts read data, and a bus acknowledge operation is controlled via the common emulator connecting-exclusive terminal with respect to the predetermined device, the bus control concerning said selected CPU core being performed via the system-bus terminal, and addresses and data input via said system-bus terminal being sent out via said common emulator connecting-exclusive terminals;

a monitor 1 mode wherein the bus control concerning said selected CPU core is performed by using the common emulator connecting-exclusive terminal;

a monitor 2 mode wherein the bus control concerning said selected CPU core is performed by using the common emulator connecting-exclusive terminal as well as the system-bus terminal for reading data; and

a monitor 3 mode wherein the bus control concerning said selected CPU core is performed by using the common emulator connecting-exclusive terminal as well as the system-bus terminal for writing data.

6. The emulation system according to claim 2, wherein, in the monitor mode when said selected CPU core is in a state where the predetermined device is to operate, said selected CPU core is in a state for receiving a hardware interrupt request and a software interrupt request, each request acting as an interrupt request from said emulator to said selected CPU core.

7. The emulation system according to claim 6, wherein the common emulator connecting-exclusive terminals include an interrupt processing input terminal for supplying therethrough a signal selectively specifying:

a reset operation substantially identical to a normal reset sequence performed by said predetermined device connected to the system-bus terminal in said selected CPU core;

an emulator NMI1 operation comprising a sequence substantially identical to a non-maskable interrupt sequence by said predetermined device, said operation resulting in generation of a unique vector number and unique vector address values that are distinct from those generated in the non-maskable interrupt sequence by said predetermined device, and said emulation NMI1 operation resulting in generation of a unique vector address without an offset value being added to said unique address values; and

an emulator NMI2 operation comprising a sequence substantially identical to the non-maskable interrupt sequence, said emulator NMI2 operation performing the interrupt processing in the selected CPU core only if a bus cycle is being carried out in said selected CPU core, said bus cycle being the one in which the relevant interrupt request occurred, and said operation resulting in generation of a unique vector number and unique vector address values that are distinct from those generated in the non-maskable interrupt sequence by said predetermined device, and said operation resulting in generation of the unique vector address without an offset value being added to said unique values.

8. The emulation system according to claim 7, wherein said interrupt processing input terminal further comprises two terminal elements for selecting one of said reset operation, said emulator NMI1 operation, said emulator NMI2 operation, and a normal mode in the absence of said reset operation, said emulator NMI1 operation and said emulator NMI2 operation.

9. The emulation system according to claim 6, wherein said software interrupt request gives rise to a sequence substantially identical to a break instruction sequence in the selected CPU core, said software interrupt request including an emulator break instruction specifying a generation of a unique vector number and unique vector address values distinct from those generated in the break instruction sequence, said emulator break instruction specifying generation of the vector address without adding an offset value to said unique vector address values.

10. The emulation system according to claim 7, wherein, in said emulator NMI1 and NMI2 operations, an automatic vector generation scheme is used and the unique vector address value is outputted.

11. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include an address/data terminal such that, as a result of multiplexing, an address is sent out via said address/data terminal in the first half of one bus cycle;

and data is sent out, after being multiplexed, via said address/data terminal in the second half of said bus cycle;

said address/data terminal, in a normal mode when said selected CPU core is not in the monitor mode, outputting independently from the read/write conditions in the selected CPU core except in the case where the emulator forcibly sends data to said selected CPU core, said address/data terminal being used for sending out therethrough data input to the system-bus terminal.

12. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include an address/status terminal for sending out therethrough, as a result of multiplexing, bit address data in the first half of one bus cycle and in the second half of said bus cycle, a status signal indicating a bus state associated with the operation currently performed by the selected CPU core.

13. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include an address/emulation-mode terminal used for sending out therethrough, as a result of multiplexing, bit address data in the first half of one bus cycle and in the second half of said bus cycle, an emulation-mode signal indicating that either the predetermined device or the emulator is currently used in said bus cycle, both being connected to the system-bus terminal.

14. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include an address/data-acknowledge terminal for sending out therethrough, as a result of multiplexing, bit address data in the first half of one bus cycle and in the second half of said bus cycle, a data acknowledge signal indicating that data transfer from the emulation bus to the selected CPU core has finished.

15. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include an address/data-acknowledge invalidating terminal for sending out therethrough, as a result of multiplexing, bit address data in the first half of one bus cycle and in the second half of said bus cycle, a data-acknowledge invalidating signal indicating that a data acknowledge signal sent from the system bus to the selected CPU core is invalid.

16. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include an address/jam terminal used for sending out therethrough, as a result of multiplexing, bit address data in the first half of one bus cycle and in the second half of said bus cycle, a jam signal indicating a forcible data input.

17. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include an address/interrupt preventing terminal for sending out therethrough, as a result of multiplexing, bit address data in the first half of one bus cycle and in the second half of said bus cycle an interrupt preventing signal indicating a prevention of an interrupt.

18. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include a read/write terminal for sending out therethrough a signal indicating the data transfer direction in the system bus as well as in the emulation bus.

19. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include a transfer data size/size acknowledge terminal for sending out therethrough, as a result of multiplexing, information concerning transferred data in the first half of one bus cycle and in the second half of said bus cycle, a size acknowledge signal indicating a port size sampled in said bus cycle in the predetermined function means connected to the system bus.

20. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include a bus-cycle start terminal for sending out therethrough a signal indicating a start of a bus cycle in synchronization with another bus cycle in the predetermined device connected to the system bus.

21. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include a data strobe terminal for sending out therethrough a signal indicating in a read cycle when the predetermined device connected to the system bus should drive said system data bus and in a write cycle when the selected CPU core is sending valid data.

22. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include a clock output terminal for sending out therethrough a clock signal which is supplied to the predetermined device connected to the system bus.

23. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include a reset output terminal for sending out therethrough a reset signal which is supplied to the predetermined device connected to the system bus.

24. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include a bus acknowledge terminal for sending out therethrough a bus acknowledge signal indicating that the predetermined device connected to the system bus associated with the selected CPU core performs a direct memory access operation, said bus acknowledge signal indicating a state when said selected CPU core surrenders the bus control right to said predetermined device.

25. The emulation system according to claim 2, wherein the common emulator connecting-exclusive terminals include a program/data/monitor mode terminal for sending out therethrough, as a result of multiplexing, a signal indicating, in the first half of one bus cycle, which of a program area and data area in an address space is accessed by the selected CPU core, said signal, in the second half of said bus cycle, controlling whether the selected CPU core is in the monitor mode.

26. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include a level/monitor mode terminal for, as a result of multiplexing, in the first half of one bus cycle, outputting a privilege level of the selected CPU core, and sending another signal, in the second half of said bus cycle, which controls whether the selected CPU core is in the monitor mode.

27. The emulation system according to claim 2, wherein said common emulator connecting-exclusive terminals include a bus-request preventing terminal for sending out therethrough a signal for preventing both a bus control right surrendering function and a bus retry function of the selected CPU core.

28. The emulation system according to claim 2, wherein the number of terminal elements provided in said common emulator connecting-exclusive terminals is smaller than a number of terminal elements provided in the system-bus terminal.

29. An application-specific IC comprising:

a CPU core arbitrarily selected from a plurality of CPU cores, each of said CPU cores having system-bus terminals and common emulator connecting-exclusive terminals, said common emulator connecting-exclusive terminals being identical in a number of terminal elements thereof and in function associated with each terminal element thereof among said plurality of said CPU cores; and

an emulator connecting-exclusive external terminal directly connected to said common emulator connecting-exclusive terminals, said emulator connecting-exclusive external terminals being provided as external terminals associated with said application-specific IC.

30. The application-specific IC according to claim 29 said external terminals include an emulation-bus use permission input terminal in addition to said common emulator connecting-exclusive terminals, said emulation-bus use permission input terminal being used for supplying therethrough a signal controlling whether or not the selected CPU core operates in a monitor mode via the common emulator connecting-exclusive terminals.

31. The application-specific IC according to claim 29, wherein said external terminals include at least one monitor-mode setting signal input terminal for supplying therethrough a signal setting a plurality of bus-control modes controlling whether the system-bus terminals or the common emulator connecting-exclusive terminals provided on the selected CPU core are selected to be given the bus control right concerning said selected CPU core.

32. A plurality of CPU cores, each of said CPU cores comprising:

system-bus terminals; and

common emulator connecting-exclusive terminals, said common emulator connecting-exclusive terminals being identical in a number of terminals thereof and functions associated with each terminal thereof among said CPU cores.

33. The plurality of different-specification CPU cores according to claim 32, further comprising an emulation-bus use permission input terminal, said emulation-bus use permission input terminal being used for supplying therethrough a signal controlling whether or not a monitor mode is operated via the common emulator connecting-exclusive terminal.

34. The plurality of different-specification CPU cores according to claim 32 further comprising at least one monitor-mode setting signal input terminal provided as an external terminal for supplying therethrough a signal which sets a plurality of predetermined bus-control modes for controlling whether the system-bus terminals or the common emulator connecting-exclusive terminals provided on the selected CPU core are selected to be given the bus control right concerning said selected CPU core.