Computer system having a serial keyboard, a serial display, and a dynamic memory with memory refresh

• US 5,594,908 A
• Filed: 01/22/1990
• Issued: 01/14/1997
• Est. Priority Date: 12/27/1989
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US07/468,430
• Time in Patent Office: 2,549 Days
• Field of Search: 395/800, 395/DIG. 1 MS File, 395/DIG. 2 MS File, 365/94-100, 365/222
• US Class Current: 710/67
• CPC Class Codes: G06F 15/00 Digital computers in general details G06F1/00 – G06F13/00; Data processing equipment in general
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

An improved computer system is provided having an integrated circuit computer, having integrated circuit (IC) memories, and having serial communication between the computer and a keyboard and between the computer and a display. Provision is made for dynamic memories with a memory refresh arrangement. Memory refresh is synchronized with computer control signals to minimize contention or conflicts with computer operations and to share control circuitry. Improved system architecture, computer architecture, and memory architecture are provided that are particularly suitable for dynamic memories and integrated circuit data processors.

Claims

1. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, the integrated circuit processor including an integrated circuit interrupt circuit that is coupled to receive an interrupt request signal, the integrated circuit interrupt circuit causing the integrated circuit processor to execute a program interrupt in response to a received interrupt request signal;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and to the integrated circuit processor and refreshing the computer operands stored by the integrated circuit dynamic MOS memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

2. A computer system as set forth in claim 1, wherein the integrated circuit read only memory is adapted to store computer operands;

wherein the integrated circuit processor includes a read only memory operand processing circuit processing one of the computer operands stored by the integrated circuit read only memory in response to a first type of computer instruction stored by the integrated circuit read only memory and includes a dynamic MOS memory operand processing circuit processing one of the computer operands stored by the integrated circuit dynamic MOS memory in response to a second type of computer instruction stored by the integrated circuit read only memory; and

wherein the serial encoder generates the serial encoded signal as a one bit wide serial data signal.

3. A computer system as set forth in claim 1, wherein the integrated circuit read only memory is adapted to store computer operands, and wherein the integrated circuit processor includes a first arithmetic circuit performing an arithmetic operation with one of the computer operands stored by the integrated circuit read only memory in response to execution of a first type of arithmetic computer instruction stored by the integrated circuit read only memory and a second arithmetic circuit performing a second arithmetic operation with one of the computer operands accessed by the dynamic memory accessing circuit in response to execution of a second type of arithmetic computer instruction stored by the integrated circuit read only memory.

4. A computer system as set forth in claim 1, wherein the integrated circuit processor includes a first transfer circuit coupled to the integrated circuit read only memory and transferring a first computer instruction stored by the integrated circuit read only memory addressed by a first instruction address operand stored by the integrated circuit read only memory, in response to execution of a first type of transfer computer instruction stored by the integrated circuit read only memory, and a second transfer circuit coupled to the integrated circuit read only memory and transferring a second computer instruction stored by the integrated circuit read only memory addressed by a second instruction address operand accessed by the dynamic memory accessing circuit in response to execution of a second type of transfer computer instruction stored by the integrated circuit read only memory.

9. A computer system as set forth in claim 1, wherein the integrated circuit dynamic MOS memory includes a plurality of memory pages storing a plurality of pages of computer instructions and computer operands;

wherein the computer system further comprises a paging circuit coupled to the integrated circuit processor and selecting at least one of the plurality of memory pages of the integrated circuit dynamic MOS memory.

11. A computer system as set forth in claim 1, further comprising a read only memory accessing circuit accessing a computer instruction stored by the integrated circuit read only memory and a dynamic memory accessing control circuit coupled to the dynamic memory accessing circuit and the read only memory accessing circuit and controlling overlapping accessing of a computer instruction stored by the integrated circuit read only memory and accessing a computer operand stored by the integrated circuit dynamic MOS memory in response to execution of an instruction by the integrated circuit processor.

12. A computer system as set forth in claim 1, wherein the integrated circuit processor includes a storing circuit storing a sixteen-bit computer instruction address in the integrated circuit dynamic MOS memory in response to execution of an eight-bit computer instruction stored by the integrated circuit read only memory.

13. A computer system as set forth in claim 1, wherein the integrated circuit read only memory is adapted to store eight-bit computer instructions, wherein the integrated circuit dynamic MOS memory includes at least one storing location storing a sixteen-bit computer operand, and wherein the processing circuit includes a sixteen bit processing circuit processing a sixteen-bit computer operand accessed by the dynamic memory accessing circuit in response to execution of one of the eight-bit computer instructions stored by the integrated circuit read only memory.

15. A computer system as set forth in claim 1, wherein the integrated circuit dynamic MOS memory is an integrated circuit dynamic MOS random access memory, wherein the integrated circuit refresh circuit refreshes the computer operands stored by the integrated circuit MOS dynamic random access memory in synchronization with execution of a stored computer instruction at a time in which the integrated circuit processor is not accessing the computer operands stored by the integrated circuit dynamic MOS memory.

5. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer operands and computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, the integrated circuit processor including an integrated circuit interrupt circuit that is coupled to receive an interrupt request signal, the integrated circuit interrupt circuit causing the integrated circuit processor to execute a program interrupt in response to a received interrupt request signal, the integrated circuit processor including a first logic circuit performing a first logical operation with a computer operand stored by the integrated circuit read only memory in response to execution of a first type of logical computer instruction stored by the integrated circuit read only memory and a second logic circuit performing a second logical operation with a computer operand accessed by the dynamic memory accessing circuit in response to execution of a second type of logical computer instruction stored by the integrated circuit read only memory;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and to the integrated circuit processor and refreshing the computer operands stored by the integrated circuit dynamic MOS memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

6. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer operands and computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, the integrated circuit processor including a first index circuit performing a first index operation with a computer operand stored by the integrated circuit read only memory in response to execution of a first type of index computer instruction stored by the integrated circuit read only memory and a second index circuit performing a second index operation with a computer operand accessed by the dynamic memory accessing circuit in response to execution of a second type of index computer instruction stored by the integrated circuit read only memory;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and to the integrated circuit processor and refreshing the computer operands stored by the integrated circuit dynamic MOS memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

7. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer operands and computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, the integrated circuit processor including a first arithmetic circuit performing a first arithmetic operation with a computer operand stored by the integrated circuit read only memory in response to execution of a multiple-byte arithmetic computer instruction stored by the integrated circuit read only memory and a second arithmetic circuit performing a second arithmetic operation with a computer operand accessed by the dynamic memory accessing circuit in response to execution of a single-byte arithmetic computer instruction stored by the integrated circuit read only memory;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and to the integrated circuit processor and refreshing the computer operands stored by the integrated circuit dynamic MOS memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

8. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer operands and computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, the integrated circuit processor including a first logic circuit performing a first logical operation with a computer operand stored by the integrated circuit read only memory in response to execution of a multiple-byte logical computer instruction stored by the integrated circuit read only memory and a second logic circuit performing a second logical operation with the computer operands accessed by the dynamic memory accessing circuit in response to execution of a single-byte logical computer instruction stored by the integrated circuit read only memory;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and to the integrated circuit processor and refreshing the computer operands stored by the integrated circuit dynamic MOS memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

10. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

a read only memory address circuit generating a read only memory address;

a read only memory accessing circuit coupled to the integrated circuit read only memory and to the read only memory address circuit, the read only memory accessing circuit accessing one of the computer instructions stored by the integrated circuit read only memory in response to the read only memory address generated by the read only memory address circuit;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, the integrated circuit processor being coupled to receive and to execute the accessed computer instruction and to receive and to process the accessed computer operands, and wherein at least a part of the time for accessing a computer instruction stored by the integrated circuit read only memory is coincident with at least a part of the time for accessing a computer operand stored by the integrated circuit dynamic MOS memory;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and to the integrated circuit processor and refreshing the computer operands stored by the integrated circuit dynamic MOS memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands;

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

14. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing eight-bit computer instructions and storing sixteen-bit computer operands;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, the integrated circuit processor including a loading circuit loading one of the sixteen-bit computer operands stored by the integrated circuit read only memory into the integrated circuit dynamic MOS memory in response to execution of at least one eight-bit computer instruction stored by the integrated circuit read only memory;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and to the integrated circuit processor and refreshing the computer operands stored by the integrated circuit dynamic MOS memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

16. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands, the integrated circuit dynamic MOS memory being an integrated circuit dynamic MOS random access memory;

an integrated circuit sequential circuit generating a sequence of control signals in response to execution of a stored computer instruction;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, the integrated circuit processor including a control signal responsive execution circuit executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the sequence of control signals generated by the integrated circuit sequential circuit;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and to the integrated circuit processor and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to at least one of the sequence of control signals generated by the integrated circuit sequential circuit;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

17. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

a refresh control circuit periodically generating a refresh signal to command refresh of the computer operands stored by the integrated circuit dynamic MOS memory;

a dynamic memory refresh circuit coupled to the integrated circuit dynamic MOS memory and to the refresh control circuit and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the refresh signal without conflict with the accessing of the computer operands by the dynamic memory accessing circuit;

a serial display refresh signal shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh display by shifting the accessed computer operands; and

the display coupled to the serial display refresh signal shift register and generating a refreshed display image in response to the serial display refresh signal.

18. A computer system as set forth in claim 17, wherein the integrated circuit dynamic MOS memory includes an integrated circuit dynamic MOS-FET shift register memory for storing the computer operands, wherein the dynamic memory refresh circuit includes a shift register recirculation circuit refreshing the computer operands stored by the integrated circuit dynamic MOS-FET shift register memory by recirculating the computer operands in response to the refresh signal, wherein the integrated circuit processor includes an instruction execution circuit adapted to process the accessed computer operands by executing the computer instructions stored by the integrated circuit read only memory, wherein the refresh control circuit includes a micro-operation circuit for periodically generating the refresh signal at a particular micro-operation word time to command the shift register recirculation circuit to refresh the integrated circuit dynamic MOS-FET shift register memory without conflict with the processing of the computer operands by the instruction execution circuit at other micro-operation word times, wherein the refresh control circuit includes a disable circuit for discontinuing processing of the computer operands stored by the integrated circuit dynamic MOS-FET shift register memory during the particular micro-operation word time to refresh the integrated circuit dynamic MOS-FET shift register memory in response to the refresh signal generated by the refresh control circuit, and wherein the integrated circuit processor includes a first instruction execution circuit coupled to the dynamic memory accessing circuit and to the serial display refresh signal shift register and inputting accessed computer operands into the serial display refresh signal shift register in response to execution of a first type of instruction by the first instruction execution circuit and includes a second instruction execution circuit coupled to the serial display refresh signal shift register and generating the serial display refresh signal to refresh the display by shifting the accessed computer operands stored by the serial display refresh signal shift register in response to execution of a second type of instruction by the second instruction execution circuit.

19. A computer system as set forth in claim 17, wherein the integrated circuit dynamic MOS memory includes an integrated circuit dynamic random access memory storing the computer operands, wherein the dynamic memory refresh circuit includes a random access memory refresh circuit refreshing the computer operands stored by the integrated circuit dynamic random access memory, wherein the integrated circuit processor includes an instruction execution circuit processing the computer operands stored by the integrated circuit dynamic random access memory by executing the computer instructions stored by the integrated circuit read only memory, wherein the refresh control circuit is arranged to periodically generate the refresh signal to command the dynamic memory refresh circuit to refresh the integrated circuit dynamic random access memory without conflict with the processing of the computer operands by the integrated circuit processor, and wherein the refresh control circuit includes a disable circuit for inhibiting processing of the computer operands stored by the integrated circuit dynamic MOS memory during the time that the integrated circuit dynamic MOS memory is refreshed in response to the refresh signal generated by the refresh control circuit, and wherein the integrated circuit processor includes a first instruction execution circuit coupled to the dynamic memory accessing circuit and to the serial display refresh signal shift register and inputting accessed computer operands into the serial display refresh signal shift register in response to execution of a first type of instruction by the first instruction execution circuit and includes a second instruction execution circuit coupled to the serial display refresh signal shift register and generating the serial display refresh signal to refresh the display by shifting the accessed computer operands stored by the serial display refresh signal shift register in response to execution of a second type of instruction by the second instruction execution circuit.

21. A computer system as set forth in claim 17, further comprising a printed circuit motherboard and at least one printed circuit logic board mounted and interconnected by the printed circuit motherboard, the printed circuit motherboard and the at least one printed circuit logic board being adapted to interconnect the integrated circuit read only memory, the integrated circuit dynamic MOS memory, the dynamic memory address generator, the dynamic memory address multiplexer, the dynamic memory accessing circuit, the integrated circuit processor, the dynamic memory refresh circuit, and the serial display refresh signal shift register.

20. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands, the integrated circuit dynamic MOS memory including a plurality of integrated circuit dynamic MOS memory chips storing the computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

an address decoder coupled to the dynamic memory address generator and generating a plurality of decoded address signals in response to the first dynamic memory address and the second dynamic memory address, each of the plurality of integrated circuit dynamic MOS memory chips being selected by at least one of the plurality of decoded address signals generated by the address decoder;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address,

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, the integrated circuit processor being coupled to process the computer operands accessed from a selected integrated circuit dynamic MOS memory chip included in the integrated circuit dynamic MOS memory in response to the at least one of the plurality of decoded address signals generated by the address decoder;

a refresh control circuit periodically generating a refresh signal to command refresh of the computer operands stored by the plurality of integrated circuit dynamic MOS memory chips included in the integrated circuit dynamic MOS memory without conflict with the processing of the computer operands by the integrated circuit processor;

a dynamic memory refresh circuit coupled to the integrated circuit dynamic MOS memory and to the refresh control circuit and refreshing the computer operands stored by the plurality of integrated circuit dynamic MOS memory chips included in the integrated circuit dynamic MOS memory in response to the refresh signal without conflict with the accessing of the computer operands by the dynamic memory accessing circuit;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

22. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

a synchronization circuit generating a memory refresh signal in synchronization with and in response to execution of one of the computer instructions by the integrated circuit processor;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and to the synchronization circuit and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the memory refresh signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

23. A computer system as set forth in claim 22, wherein the integrated circuit processor and the synchronization circuit are implemented on multiple integrated circuit chips and wherein the serial keyboard signal generated by the keyboard serial encoder is a serial by bit keyboard signal.

24. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing eight-bit instructions;

an integrated circuit dynamic MOS memory storing sixteen-bit computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing sixteen-bit computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the eight-bit, an integrated circuit processor coupled to the integrated circuit read only memory, coupled to the dynamic memory accessing circuit, and coupled to the serial interface circuit, the integrated circuit processor processing the sixteen-bit computer operands accessed by the dynamic memory accessing circuit in response to execution of the eight-bit instructions stored by the integrated circuit read only memory;

a synchronization circuit generating a memory refresh signal in synchronization with and in response to execution of an eight-bit instruction by the integrated circuit processor;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and to the synchronization circuit and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the memory refresh signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

25. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

the integrated circuit processor being coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

an integrated circuit processor including;

a single byte accessing circuit accessing a single byte instruction stored by the integrated circuit read only memory,

a single byte execution circuit executing the single byte instruction accessed by the single byte accessing circuit,

a double byte accessing circuit accessing a double byte instruction stored by the integrated circuit read only memory,

a double byte execution circuit executing the double byte instruction accessed by the double byte accessing circuit,

a triple byte accessing circuit accessing a triple byte instruction stored by the integrated circuit read only memory, and

a triple byte execution circuit executing the triple byte instruction accessed by the triple byte accessing circuit

a synchronization circuit generating a memory refresh signal in synchronization with and in response to execution of an instruction by the integrated circuit processor;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and to the synchronization circuit and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the memory refresh signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

26. A computer system as set forth in claim 25, wherein the integrated circuit processor includes a loading circuit loading a computer operand into the integrated circuit dynamic MOS memory in response to execution of a load instruction stored by the integrated circuit read only memory and wherein the serial keyboard signal generated by the keyboard serial encoder is a serial by bit keyboard signal.

27. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to receive the keyboard switch signals from the keyboard switches and generating the serial keyboard signal representing the received keyboard switch signals in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address in response to the first dynamic memory address and in response to the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, wherein the integrated circuit processor includes an integrated circuit sequential circuit generating a sequence of control signals in response to the execution of the computer instructions;

an integrated circuit refresh circuit coupled to the integrated circuit dynamic MOS memory and to the integrated circuit sequential circuit and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to at least one of the sequence of control signals;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

28. A computer system as set forth in claim 27, wherein the integrated circuit dynamic MOS memory includes a MOS-FET integrated circuit shift register memory storing the computer operands.

29. A computer system as set forth in claim 27, further comprising a printed circuit board, wherein the integrated circuit processor is an all integrated circuit processor implemented on a plurality of integrated circuit chips mounted and interconnected on the printed circuit board, and wherein the integrated circuit dynamic MOS memory is implemented on a plurality of integrated circuit dynamic memory chips mounted and interconnected on the printed circuit board.

30. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer instructions;

an alterable integrated circuit memory storing computer operands;

an integrated circuit processor coupled to the integrated circuit read only memory, to the alterable integrated circuit memory and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the computer operands accessed from the alterable integrated circuit memory in response to the computer input signal, wherein the integrated circuit processor includes;

1) a processor control circuit generating a sequence of control signals in response to the execution of an instruction, and

2) a processing circuit coupled to the processor control circuit and processing an accessed computer operand in response to at least one of the control signals in the sequence of control signals;

a dynamic memory refresh circuit coupled to the alterable integrated circuit memory and to the processor control circuit and refreshing the computer operands stored by the alterable integrated circuit memory in response to at least one of the control signals in the sequence of control signals;

a shift register coupled to receive a computer operand from the alterable integrated circuit memory and generating a serial display refresh signal to refresh a display by shifting the received computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

31. A computer system as set forth in claim 30, wherein the alterable integrated circuit memory includes a register storing alterable information in response to the refresh signal and wherein the serial encoded signal and the serial display refresh signal are each one bit wide serial data signals.

32. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer instructions;

an alterable integrated circuit memory storing computer operands, the alterable integrated circuit memory including;

an address generator generating an operand address having more significant address bits and less significant address bits,

a first address decoder coupled to the address generator and generating a first decoded address in response to the more significant address bits,

a second address decoder coupled to the address generator and generating a second decoded address in response to the less significant address bits, and

an accessing circuit coupled to the alterable integrated circuit memory, to the first address decoder, and to the second address decoder and accessing one of the computer operands in response to the first decoded address and in response to the second decoded address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the alterable integrated circuit memory and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process computer operands accessed from the alterable integrated circuit memory in response to the computer input signal, wherein the integrated circuit processor includes;

1) a processor control circuit generating a sequence of control signals in response to the execution of an instruction, and

2) a processing circuit coupled to the processor control circuit and processing an accessed computer operand in response to at least one of the control signals in the sequence of control signals;

a dynamic memory refresh circuit coupled to the alterable integrated circuit memory and to the processor control circuit and refreshing the computer operands stored by the alterable integrated circuit memory in response to the at least one of the control signals in the sequence of control signals;

a shift register coupled to receive a computer operand from the alterable integrated circuit memory and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

33. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the plurality of keyboard switches and generating the serial keyboard signal representing the keyboard switch signals in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address in response to the first dynamic memory address and in response to the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

a refresh control circuit periodically generating a refresh signal to command refresh of the computer operands stored by the integrated circuit dynamic MOS memory;

a dynamic memory refresh circuit coupled to the integrated circuit dynamic MOS memory and to the refresh control circuit and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the refresh signal without conflict with the processing of the computer operands by the integrated circuit processor;

a disable circuit coupled to the dynamic memory accessing circuit and to the refresh control circuit and disabling the accessing of the computer operands during refreshing of the dynamic MOS memory in response to the refresh signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

34. A computer system as set forth in claim 33, wherein the integrated circuit dynamic MOS memory is adapted to store computer instructions, wherein the dynamic memory accessing circuit is adapted to access computer instructions from the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address, wherein the integrated circuit processor is adapted to process accessed computer operands in response to accessed computer instructions and wherein the serial keyboard signal is a one bit wide serial keyboard signal.

35. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to receive the serial encoded signal and generating computer input information in response to the serial encoded signal;

integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address in response to the first dynamic memory address and in response to the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

a refresh control circuit generating a refresh signal to command refreshing of the integrated circuit dynamic MOS memory during a time interval that does not conflict with the processing of the computer operands by the integrated circuit processor;

a dynamic memory refresh circuit coupled to the refresh control circuit and to the integrated circuit dynamic MOS memory and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the refresh signal during the time interval that does not conflict with the accessing of the computer operands by the dynamic memory accessing circuit;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

36. A computer system as set forth in claim 35, further comprising an address decoder coupled to the dynamic memory address generator and generating a plurality of decoded address signals in response to the first memory address and the second memory address;

and wherein the integrated circuit dynamic MOS memory includes a plurality of integrated circuit dynamic MOS memory chips storing the computer operands, wherein each of the plurality of integrated circuit dynamic MOS memory chips is selected by at least one of the plurality of decoded address signals generated by the address decoder, wherein the dynamic memory refresh circuit is coupled to refresh the computer operands stored by the plurality of integrated circuit dynamic MOS memory chips included in the integrated circuit dynamic MOS memory in response to the refresh signal, wherein the integrated circuit processor is coupled to receive from the integrated circuit dynamic MOS memory and to process computer operands stored by a selected integrated circuit dynamic MOS memory chip included in the integrated circuit dynamic MOS memory in response to a decoded address signal generated by the address decoder, and wherein the refresh control circuit periodically generates the refresh signal to refresh the plurality of integrated circuit dynamic MOS memory chips included in the integrated circuit dynamic MOS memory without conflict with the receiving of the computer operands by the integrated circuit integrated circuit processor.

37. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to receive the keyboard switch signals from the keyboard switches and generating the serial keyboard signal in response to the received keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

an integrated circuit refresh circuit coupled to the integrated circuit dynamic MOS memory and to the integrated circuit processor and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to execution of the computer instructions by the integrated circuit processor;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display in response to the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

38. A computer system according to claim 37 wherein the integrated circuit dynamic MOS memory requires a refresh signal to be provided at a rate at least as high as a minimum refresh rate to preserve the computer operands stored therein;

wherein the instruction execution rate is at least as high as the minimum refresh rate; and

wherein the serial display refresh signal is generated in response to execution of one of the computer instructions stored by the integrated circuit read only memory.

39. A computer system comprising:

a plurality of operator switches generating switch signals;

a combining circuit coupled to the plurality of operator switches and generating switch information representing the switch signals in response to the switch signals;

an interface circuit coupled to receive switch information generated by the combining circuit and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor processing computer operands, the integrated circuit processor including;

1) an integrated circuit instruction execution control circuit coupled to the integrated circuit read only memory and generating a sequence of instruction execution control signals to execute a computer instruction stored by the integrated circuit read only memory, and

2) an integrated circuit processing circuit coupled to the dynamic memory accessing circuit, to the integrated circuit instruction execution control circuit, and to the serial interface circuit and processing the accessed computer operands in response to the sequence of instruction execution control signals and in response to the computer input signal;

a refresh control circuit coupled to the integrated circuit instruction execution control circuit and generating a refresh control signal after completion of the sequence of instruction execution control signals;

a refresh execution circuit coupled to receive the refresh control signal from the refresh control circuit and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the received refresh control signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

40. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor processing computer operands, the integrated circuit processor including;

1) an instruction execution control circuit coupled to the integrated circuit read only memory and generating a sequence of instruction execution control signals to execute one of the computer instructions stored by the integrated circuit read only memory,

2) a refresh control circuit coupled to the integrated circuit execution control circuit and generating a refresh signal following the generation of the sequence of instruction execution control signals, and

3) an instruction execution circuit coupled to the integrated circuit instruction execution control circuit, to the dynamic memory accessing circuit, and to the serial interface circuit and processing the accessed computer operands in response to the sequence of instruction execution control signals and in response to the computer input signal;

a refresh execution circuit coupled to the integrated circuit dynamic MOS memory and to the refresh control circuit and refreshing the integrated circuit dynamic MOS memory in response to the refresh signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

41. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to receive the serial keyboard signal from the keyboard serial encoder and generating the computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

a refresh circuit coupled to the integrated circuit dynamic MOS memory to refresh the integrated circuit dynamic MOS memory without conflicting with execution by the integrated circuit processor of the computer instructions stored by the integrated circuit read only memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

42. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

a clock generator circuit generating a clock signal;

a clock gating flip-flop coupled to receive the clock signal and generating a clock gating signal in response thereto;

a clock gating circuit coupled to the clock generator circuit and to the clock gating flip-flop and generating a gated clock signal in response to the clock signal and the clock gating signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, to the serial interface circuit, and to the clock gating circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the gated clock signal and in response to the computer input signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

43. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal representing the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit read only memory storing computer instructions and instruction address operands;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, wherein the integrated circuit processor includes;

1) a first processing circuit coupled to the integrated circuit read only memory and transferring one of the computer instructions stored by the integrated circuit read only memory at an address indicated by one of the instruction address operands stored by the integrated circuit read only memory in response to execution of a transfer computer instruction stored by the integrated circuit read only memory,

2) a second processing circuit coupled to the dynamic memory accessing circuit and to the read only memory and transferring one of the computer instructions stored by the integrated circuit read only memory at an address indicated by one of the instruction address operands accessed by the dynamic memory accessing circuit in response to execution of an indirect transfer computer instruction stored by the integrated circuit read only memory, and

3) a refresh circuit generating a dynamic memory refresh signal in response to execution of at least one of the computer instructions stored by the integrated circuit read only memory;

a refresh circuit refreshing data stored by the integrated circuit dynamic MOS memory in response to the dynamic memory refresh signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

44. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, wherein the integrated circuit processor includes;

1) a micro-instruction circuit executing a plurality of micro-instructions in response to execution of one of the computer instructions stored by the integrated circuit read only memory,

2) a processing circuit coupled to the dynamic memory accessing circuit and to the micro-instruction circuit and processing the accessed computer operands in response to execution of at least one of the micro-instructions, and

3) a synchronization circuit generating a dynamic memory refresh signal synchronized with execution of an instruction responsive micro-instruction;

a dynamic memory refresh circuit coupled to the integrated circuit dynamic MOS memory and to the synchronization circuit and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the dynamic memory refresh signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

45. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, wherein the integrated circuit processor includes;

1) a micro-operation circuit coupled to the integrated circuit read only memory and generating a plurality of sequential micro-operation signals by execution of one of the computer instructions stored by the integrated circuit read only memory,

2) a processing circuit coupled to the dynamic memory accessing circuit and to the micro-operation circuit and processing the accessed computer operands in response to the plurality of sequential micro-operation signals, and

3) a synchronization circuit coupled to the micro-operation circuit and generating a dynamic memory refresh signal in synchronization with and in response to the plurality of the micro-operation signals;

a dynamic memory refresh circuit coupled to the integrated circuit dynamic MOS memory and to the synchronization circuit and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the dynamic memory refresh signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal to refresh a display by shifting the accessed computer operands; and

the display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

46. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal representing the keyboard switch signals in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address in response to the first dynamic memory address and in response to the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

a refresh circuit control circuit periodically generating a refresh signal to command refresh of the computer operands stored by the integrated circuit dynamic MOS memory without conflict with the processing of the computer operands by the integrated circuit processor;

an integrated circuit refresh circuit coupled to the integrated circuit dynamic MOS memory and to the refresh control circuit and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the refresh signal without conflict with the processing of the computer operands by the integrated circuit processor;

a disable circuit coupled to the integrated circuit processor and to the refresh control circuit to disable the processing of the computer operands by the integrated circuit processor during refreshing of the integrated circuit dynamic MOS memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

47. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address, each having a plurality of less significant bits and a plurality of more significant bits;

a memory address detector circuit coupled to the dynamic memory address generator and generating a memory address detector signal in response to detection of a selected state among the plurality of more significant bits;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory coupled to the memory address detector circuit and storing computer operands in response to the memory address detector signal;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address in response to the first dynamic memory address and in response to the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an instruction execution control circuit generating a sequence of instruction execution control signals to control execution of one of the computer instructions stored by the integrated circuit read only memory;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, to the instruction execution control circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the sequence of instruction execution control signals and in response to the computer input signal;

a refresh control circuit coupled to the instruction execution control circuit, the refresh control circuit generating a refresh control signal after completion of the generation of the sequence of instruction execution control signals by the instruction execution control circuit;

a refresh execution circuit coupled to the integrated circuit dynamic MOS memory and to the refresh control circuit and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the refresh control signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

48. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an interrupt request circuit generating an interrupt request signal;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address in response to the first dynamic memory address and in response to the second dynamic memory address;

an address decoder coupled to the dynamic memory address generator and generating a plurality of decoded address signals in response to the first memory address and in response to the second memory address;

an integrated circuit read only memory storing computer instructions;

a MOS integrated circuit dynamic random access memory coupled to the address decoder and storing computer operands, the MOS integrated circuit dynamic random access memory including a plurality of integrated circuit dynamic random access memory chips storing the computer operands, each of the plurality of integrated circuit dynamic random access memory chips being selected by at least one of the plurality of decoded address signals generated by the address decoder;

a dynamic memory accessing circuit coupled to the MOS integrated circuit dynamic random access memory chips and to the dynamic memory address multiplexer and accessing computer operands stored by a selected integrated circuit dynamic random access memory chip in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the serial interface circuit, to the integrated circuit read only memory, and to the dynamic memory accessing circuit and executing the computer instructions stored by the integrated circuit read only memory to process the computer operands accessed from the selected integrated circuit dynamic random access memory chip included in the MOS integrated circuit dynamic random access memory in response to the at least one of the plurality of decoded address signals generated by the address decoder and in response to the computer input signal, the integrated circuit processor including an integrated circuit interrupt circuit coupled to receive the interrupt request signal generated by the interrupt request circuit, the interrupt circuit causing the integrated circuit processor to begin processing instructions at a different location in the integrated circuit read only memory in response to a received interrupt request signal, the integrated circuit processor also including an integrated circuit interrupt return circuit, the interrupt return circuit causing the integrated circuit processor to return from a previously executed interrupt in response to execution of an instruction by the integrated circuit processor;

a refresh circuit coupled to the MOS integrated circuit dynamic random access memory and periodically refreshing the plurality of dynamic random access memory chips included in the MOS integrated circuit dynamic random access memory without conflicting with execution by the integrated circuit processor of a computer instruction stored by the integrated circuit read only memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

49. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal representing the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit MOS dynamic random access memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address in response to the first dynamic memory address and in response to the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit MOS dynamic random access memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit MOS dynamic random access memory in response to the multiplexed dynamic memory address;

a micro-operation circuit coupled to the integrated circuit read only memory and generating micro-operation signals including instruction execution micro-operation signals and a refresh micro-operation signal in response to execution of computer instructions stored by the integrated circuit read only memory;

an integrated circuit processor coupled to the micro-operation circuit, to the dynamic memory accessing circuit, and to the serial interface circuit and processing the accessed computer operands in response to the instruction execution micro-operation signals and the computer input signal;

a refresh circuit coupled to the micro-operation circuit and refreshing the integrated circuit MOS dynamic random access memory in response to the refresh micro-operation signal without conflicting with the execution of computer instructions by the integrated circuit processor;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

50. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

a MOS integrated circuit dynamic random access memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the MOS integrated circuit dynamic random access memory and to the dynamic memory address multiplexer and accessing computer operands stored by the MOS integrated circuit dynamic random access memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the serial interface circuit, to the integrated circuit read only memory, and to the dynamic memory accessing circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands memory in response to the computer input signal;

a refresh circuit coupled to refresh the MOS integrated circuit dynamic random access memory without conflicting with execution of one of the computer instructions stored by the integrated circuit read only memory by the integrated circuit processor;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

51. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the serial interface circuit, to the integrated circuit read only memory, and to the dynamic memory accessing circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

a refresh circuit which refreshes the integrated circuit dynamic MOS memory without conflicting with execution of a computer instruction by the integrated circuit processor by disabling execution of the computer instructions stored by the integrated circuit read only memory during refreshing of the integrated circuit dynamic MOS memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

52. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

a MOS integrated circuit dynamic random access memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address in response to the first dynamic memory address and in response to the second dynamic memory address;

a dynamic memory accessing circuit coupled to the MOS integrated circuit dynamic random access memory and to the dynamic memory address multiplexer and accessing computer operands stored by the MOS integrated circuit dynamic random access memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the serial interface circuit, to the integrated circuit read only memory, and to the dynamic memory accessing circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

a refresh circuit coupled to refresh the MOS integrated circuit dynamic random access memory without conflicting with execution of a computer instruction by the integrated circuit processor by inhibiting execution of the computer instructions by the integrated circuit processor during refreshing of the MOS integrated circuit dynamic random access memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

53. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

a MOS integrated circuit dynamic random access memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit coupled to the MOS integrated circuit dynamic random access memory and to the dynamic memory address multiplexer and accessing computer operands stored by the MOS integrated circuit dynamic random access memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal, the integrated circuit processor including an integrated circuit sequential circuit generating a sequence of control signals in response to execution of a stored computer instruction;

an integrated circuit refresh circuit coupled to the MOS integrated circuit dynamic random access memory and to the integrated circuit sequential circuit and refreshing the computer operands stored by the MOS integrated circuit dynamic random access memory in response to at least one of the sequence of control signals;

a disable circuit coupled to the integrated circuit processor to disable the processing of the computer operands by the accessed integrated circuit processor during refreshing of the computer operands stored by the MOS integrated circuit dynamic random access memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

54. A computer system comprising:

a plurality of operator switches generating switch signals;

a serial encoder coupled to the plurality of operator switches and generating a serial encoded signal having the switch signals encoded therein in response to the switch signals;

a serial interface circuit coupled to the serial encoder and generating a computer input signal in response to the serial encoded signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address in response to the first dynamic memory address and in response to the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

a refresh control circuit coupled to the integrated circuit processor and generating a refresh signal at selected intervals of time synchronized to the execution of instructions by the integrated circuit processor;

a refresh execution circuit coupled to the refresh control circuit and refreshing the integrated circuit dynamic MOS memory in response to the refresh signal;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

55. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal representing the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

a integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address in response to the first dynamic memory address and in response to the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the computer operands accessed by the dynamic memory accessing circuit in response to the computer input signal;

a refresh circuit coupled to refresh the integrated circuit dynamic MOS memory with sufficient frequency to retain data stored by the integrated circuit dynamic MOS memory;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

56. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals encoded therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

an integrated circuit read only memory storing computer instructions;

an integrated circuit dynamic MOS memory storing computer operands;

a dynamic memory address generator generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer coupled to the dynamic memory address generator and generating a multiplexed dynamic memory address in response to the first dynamic memory address and in response to the second dynamic memory address;

a dynamic memory accessing circuit coupled to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor coupled to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

a refresh circuit coupled to the integrated circuit dynamic MOS memory and refreshing the integrated circuit dynamic MOS memory with sufficient frequency to retain data stored by the integrated circuit dynamic MOS memory and coupled to inhibit communication of data between the integrated circuit dynamic MOS memory and the integrated circuit processor while the integrated circuit dynamic MOS memory is being refreshed;

a shift register coupled to the dynamic memory accessing circuit and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.

57. A computer system comprising:

a keyboard generating a serial keyboard signal, wherein the keyboard includes;

1) a plurality of keyboard switches generating keyboard switch signals, and

2) a keyboard serial encoder coupled to the keyboard switches and generating the serial keyboard signal having the keyboard switch signals represented therein in response to the keyboard switch signals;

a serial interface circuit coupled to the keyboard serial encoder and generating a computer input signal in response to the serial keyboard signal;

a printed circuit motherboard and at least one printed circuit logic board mounted and interconnected by the printed circuit motherboard and adapted to interconnect circuitry;

an integrated circuit read only memory interconnected by the printed circuit motherboard and the at least one printed circuit logic board and storing computer instructions;

an integrated circuit dynamic MOS memory interconnected by the printed circuit motherboard and the at least one printed circuit logic board and storing computer operands;

a dynamic memory address generator interconnected by the printed circuit motherboard and the at least one printed circuit logic board and generating a first dynamic memory address and a second dynamic memory address;

a dynamic memory address multiplexer interconnected to the dynamic memory address generator by the printed circuit motherboard and the at least one printed circuit logic board and generating a multiplexed dynamic memory address by multiplexing the first dynamic memory address and the second dynamic memory address;

a dynamic memory accessing circuit interconnected to the integrated circuit dynamic MOS memory and to the dynamic memory address multiplexer by the printed circuit motherboard and the at least one printed circuit logic board and accessing computer operands stored by the integrated circuit dynamic MOS memory in response to the multiplexed dynamic memory address;

an integrated circuit processor interconnected to the integrated circuit read only memory, to the dynamic memory accessing circuit, and to the serial interface circuit by the printed circuit motherboard and by the at least one printed circuit logic board and executing the computer instructions stored by the integrated circuit read only memory to process the accessed computer operands in response to the computer input signal;

an integrated circuit refresh control circuit periodically generating a refresh signal to command refresh of the computer operands stored by the integrated circuit dynamic MOS memory;

an integrated circuit memory refresh circuit interconnected to the integrated circuit dynamic MOS memory and to the integrated circuit refresh control circuit by the printed circuit motherboard and the at least one printed circuit logic board and refreshing the computer operands stored by the integrated circuit dynamic MOS memory in response to the refresh signal without conflict with the processing of the computer operands by the integrated circuit processor;

a shift register interconnected to the dynamic memory accessing circuit by the printed circuit motherboard and the at least one printed circuit logic board and generating a serial display refresh signal by shifting the accessed computer operands; and

a display coupled to the shift register and generating a refreshed display image in response to the serial display refresh signal.