Neural network processing system using semiconductor memories and processing paired data in parallel

• US 5,594,916 A
• Filed: 01/04/1995
• Issued: 01/14/1997
• Est. Priority Date: 01/24/1990
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Kimura, Katsutaka, Watanabe, Takao, Kawajiri, Yoshiki, Itoh, Kiyoo
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/369,163
• Time in Patent Office: 741 Days
• Field of Search: 395/800, 395/27, 395/477
• US Class Current: 711/150
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A data processing system has a memory for realizing large-scale and high-speed parallel distributed processing and, especially, a data processing system for neural network processing. The neural network processing system comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operation of the memory circuit, the input/output circuit and the processing circuit. The processing circuit includes at least one of an address, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neuron output values such as the product of sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neurons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

Claims

1. A data processing system constructed on a semiconductor chip, the data processing system comprising:

a memory having a plurality of data lines, a plurality of word lines arranged to intersect with said plurality of data lines and a plurality of memory cells each formed at an intersection of a one of said plurality of data lines and a one of said plurality of word lines;

a word line selector for selectively selecting a one of said word lines; and

,

a plurality of processing circuits associated with said plurality of data lines for collectively executing a parallel processing on a pair of data items wherein said pair are sequentially output on a one of said plurality of data lines, said pair comprising a first data item and a second data item with the first data item being different from the second data item, each of said plurality of processing circuits including a register for storing first data comprising the first data item which is output through said one of said plurality of data lines to a corresponding one of said plurality of processing circuits from a first memory cell connected with the selected one of said plurality of word lines, and wherein each of said plurality of processing circuits includes means for executing an arithmetic processing according to the stored first data in the register simultaneously with an output of second data corresponding to the second data item on said one of said plurality of data lines corresponding to said one of said plurality of processing circuits from a second memory cell connected with a selected second word line of said plurality of word lines.

2. The data processing system according to the claim 1 further comprising:

a data write means for writing output data of said plurality of processing circuits into said memory.

3. The data processing system according to the claim 1 further comprising:

a read/write means for i) reading data from said memory and delivering the read data to an output of said semiconductor chip and ii) writing data from outside of said semiconductor chip into said memory.