Method and apparatus determining order and identity of subunits by inputting bit signals during first clock period and reading configuration signals during second clock period

• US 5,594,925 A
• Filed: 01/05/1993
• Issued: 01/14/1997
• Est. Priority Date: 01/05/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Harder, Stanley D., Houghton, Richard A., Wallace, Richard H.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Kim, Sang Hui
• Application Number:
  US08/000,755
• Time in Patent Office: 1,470 Days
• Field of Search: 395/275, 395/827, 395/844, 395/845, 395/863, 395/865, 395/878, 395/836, 395/837
• US Class Current: 710/43
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

A unit train (10) includes a base unit (12). Base unit (12) generates a clock signal and a bit signal. Base unit (12) also receives and interprets a data signal. Unit train (10) also includes a plurality of subunits (14) serially coupled in a certain order. Each subunit (14) receives the clock signal and the bit signal. Each subunit (14) also generates a portion of the data signal. Additionally each of the subunits (14) has a corresponding identity. Also included in the unit train (10) is a clock/data line (67) for relaying the clock signal and the data signal between the base unit (12) and each subunit (14).

Claims

1. A unit train comprising:

a base unit comprising

a bit generator for generating a bit pulse,

a clock for generating a clock signal having first and second clock periods,

a bit signal line and a single clock/data line, and

an interpreter circuit coupled to the bit generator and the clock and responsive to couple the bit generator to output a ONE bit pulse on the bit signal line, and afterward responsive during the first clock period to couple the clock signal as output to the clock/data line only during the first clock period, and during the second period to couple itself to the clock/data line for input only of a subunit configuration data signal; and

a plurality of subunits responsive to the bit generator and clock for generating the subunit configuration data signal, each subunit comprising

a shift register having N bit positions, coupled in parallel to the clock and in series to the bit signal line, and

a logic unit coupled for input to the shift register at preselected bit positions identifying the particular subunit and coupled in parallel for outputting a ZERO on the clock/data line during the second clock period whenever there is a ONE in any of the preselected bit positions of the shift register.

2. The unit train of claim 1 wherein said base unit further comprises an interface for periodically uncoupling said clock signal from said clock/data line such that said base unit receives said data signal when said clock signal is uncoupled from said clock/data line.

3. The unit train of claim 2 wherein said interface device comprises a switch, responsive to said interpreter, for periodically uncoupling said clock signal from said clock/data line.

4. The unit train of claim 1 wherein the base unit further comprises an interpreter, responsive to said data signal, for determining said corresponding identity of each of said plurality of subunits and for determining said certain order.

5. The unit train of claim 1 wherein each of said plurality of subunits further comprises:

a register circuit for receiving said bit signal; and

a logic unit array, responsive to said register circuit, for generating said portion of said data signal.

6. The unit train of claim 5 wherein said register circuit comprises a shift register, responsive to said clock signal and having a plurality of bit positions, for shifting said bit signal through said plurality of bit positions.

7. The unit train of claim 6 wherein said shift register shifts said bit signal from a last one of said plurality of bit positions to a first one of a plurality of bit positions of a second shift register in a second one of said plurality of subunits.

8. The unit train of claim 6 wherein said logic unit array comprises at least one logic unit responsive to one of said plurality of bit positions to generate said portion of said data signal.

9. The unit train of claim 8 wherein said at least one logic unit comprises a switch for generating said portion of said data signal by coupling a reference voltage to said clock/data line.

10. A method for using a number of subunits, serially coupled in a certain order, each subunit having a certain identity, to determine the certain order and the certain identity of each subunit comprising the steps of:

providing a bit generator for generating a bit pulse;

providing a clock for generating a clock signal having first and second clock periods;

providing a bit signal line and a single clock/data line;

providing an interpreter circuit coupled to the bit generator and the clock and responsive to couple the bit generator to output a ONE bit pulse on the bit signal line, and afterward responsive during the first clock period to couple the clock signal as output to the clock/data line only during the first clock period, and during the second period to couple itself to the clock/data line for input only of a subunit configuration data signal; and

providing a plurality of subunits responsive to the bit generator and clock for generating the subunit configuration data signal.

11. The method of claim 10, wherein each subunit comprises a shift register having N bit positions, coupled in parallel to the clock and in series to the bit signal line.

12. A method for using a number of subunits, serially coupled in a certain order, each subunit having a certain identity, to determine the certain order and the certain identity of each subunit comprising the steps of:

providing a bit generator for generating a bit pulse;

providing a clock for generating a clock signal having first and second clock periods;

providing a bit signal line and a single clock/data line;

providing an interpreter circuit coupled to the bit generator and the clock and responsive to couple the bit generator to output a ONE bit pulse on the bit signal line, and afterward responsive during the first clock period to couple the clock signal as output to the clock/data line only during the first clock period, and during the second period to couple itself to the clock/data line for input only of a subunit configuration data signal; and

providing a plurality of subunits responsive to the bit generator and clock for generating the subunit configuration data signal, each subunit comprising a shift register having N bit positions, coupled in parallel to the clock and in series to the bit signal line, and a logic unit coupled for input to the shift register at preselected bit positions identifying the particular subunit and coupled in parallel for outputting a ZERO on the clock/data line during the second clock period whenever there is a ONE in any of the preselected bit positions of the shift register.