Technique of forming over an irregular surface a polysilicon layer with a smooth surface

• US 5,595,924 A
• Filed: 12/19/1994
• Issued: 01/21/1997
• Est. Priority Date: 05/25/1994
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Yuan, Jack H., Samachisa, Gheorghe
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/358,801
• Time in Patent Office: 764 Days
• Field of Search: 437/43, 437/233, 437/69, 437/52, 437/48, 437/67, 437/193, 437/228, 437/186
• US Class Current: 438/587
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: Y10S 438/917 Deep level dopants, e.g. gold, chromium, iron or nickel
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

Claims

1. A method of forming a structure on an integrated circuit substrate, comprising the steps of:

depositing a layer of field oxide on said substrate,

etching channels in said field oxide layer,

depositing a layer of polysilicon across the field oxide and the channels to a thickness wherein a top surface of the polysilicon layer is substantially smooth across the channels,

oxidizing the polysilicon layer top surface to a uniform depth thereacross, and

stripping away the oxidized polysilicon material, thereby to leave a polysilicon layer with a substantially smooth surface across the channels.

2. A method according to claim 1, wherein the step of etching channels in said field oxide includes anisotropically etching said field oxide, thereby forming said channels with sharp sidewalls, the method further comprising a step of forming spacers along said sidewalls prior to the step of depositing the polysilicon layer.

3. A method according to claim 1, which additionally comprises, after the step of stripping away the oxidized polysilicon material, separating the polysilicon layer into an array of floating transistor gates.

4. A method according to claim 1, wherein the step of etching channels in said field oxide includes orienting said channels with lengths extending in a first direction and being spaced apart in a second direction, said first and second directions being perpendicular to each other, the method further comprising, after the step of stripping away the oxidized polysilicon material, separating the polysilicon layer into a plurality of elongated strips having lengths extending in the second direction and being spaced apart in the first direction.

5. A method according to claim 1, which additionally comprises the steps of forming a dielectric over the smooth polysilicon layer surface, and thereafter depositing a second polysilicon layer on the dielectric.

6. A method of forming a structure on an integrated circuit substrate, comprising:

depositing a layer of dielectric material supported by said substrate,

forming channels in the dielectric layer by removing portions thereof according to a pattern,

forming a layer of polysilicon material over the dielectric layer and extending into the channels, said polysilicon layer having a thickness T over the dielectric layer such that, if the polysilicon layer was deposited only to said thickness T, the polysilicon layer would have depressions in a top surface thereof over the channels, the polysilicon layer forming step including;

depositing said layer of polysilicon to a thickness in excess of T over the dielectric layer until the top surface of the polysilicon no longer contains said depressions, and

removing a portion of the polysilicon layer until its thickness over the dielectric layer is equal to T.

7. A method according to claim 6, wherein removing a portion of the polysilicon layer includes oxidizing the polysilicon layer top surface, and stripping away the oxidized polysilicon.

8. A method according to claim 6, which additionally comprises forming a second dielectric layer over a top surface of the polysilicon layer after the portion thereof has been removed, and thereafter forming a second layer of polysilicon on the second dielectric layer.