Method for making self-aligned source/drain mask ROM memory cell using trench etched channel

• US 5,595,927 A
• Filed: 03/17/1995
• Issued: 01/21/1997
• Est. Priority Date: 03/17/1995
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ling, Sung, Hung-Cheng, Lo, Chi-Shiung
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/405,722
• Time in Patent Office: 676 Days
• Field of Search: 437/52, 437/53, 437/40 SW, 437/41 SW, 437/203, 148/DIG. 106
• US Class Current: 438/270
• CPC Class Codes: H10B 20/40 having the source region and drain region on different levels, e.g. vertical channel

Abstract

A device and a method are provided for manufacture of that semiconductor memory device on a silicon semiconductor substrate with a vertical channel. A dielectric layer pattern with openings through it is formed. Trenches are formed in the surface of the semiconductor substrate. The trenches have sidewalls. A spacer layer is formed on the surface of the device. The spacer layer is shaped to form spacers in the trenches on the sidewalls. Source/drain regions are formed by ion implanting ions to deposit dopant into the substrate. The device is annealed to form source/drain regions in the substrate. A dielectric layer is formed over the device. A conductive word-line is formed and patterned over the dielectric layer.

Claims

1. A method of manufacture of a semiconductor memory device including a silicon semiconductor substrate with a vertical channel comprising the sequence of steps as follows:

forming a first dielectric masking layer patterned with pattern of trench openings therethrough on said substrate,

etching of trenches in the surface of the semiconductor substrate through said first dielectric masking layer,

said trenches having bases and sidewalls, said substrate having upper surfaces between and/or aside from said trenches,

removing said masking layer,

forming a sub-spacer layer on the surface of said device,

forming a spacer layer over said sub-spacer dielectric layer,

shaping said spacer layer to form spacers over said sub-spacer dielectric layer in said trenches along said sidewalls,

ion implanting source/drain ions to deposit dopant in said substrate,

removing said spacer layer and said sub-spacer layer from said device,

forming a silicon dioxide layer over said device,

source/drain annealing said device to form source/drain regions in said silicon semiconductor substrate, and

forming and patterning a conductive word-line over said dielectric layer.

2. The method of claim 1 wherein

said trenches are formed by forming said first dielectric layer for masking comprising a silicon dioxide layer on said silicon substrate, and forming a photoresist mask on said masking silicon dioxide layer,

etching said masking silicon dioxide layer through said photoresist mask to form a trench mask in said masking silicon dioxide layer, and

etching of said silicon through said trench mask formed by said masking silicon dioxide layer to form said trench.

3. The method of claim 2 wherein said spacers are formed by the steps comprising

removing said masking silicon dioxide layer,

forming said sub-spacer of a dielectric layer comprising silicon dioxide over said device including said trenches,

forming said spacer layer composed of a material selected from the group consisting of polysilicon and silicon nitride over said sub-spacer dielectric layer, and

then etching said spacer layer to form said spacers.

4. The method of claim 3 wherein subsequent to formation of said spacers the step fellows comprising,

performing said source/drain ion implantation as a self-aligned ion implantation with ions composed of a dopant selected from the group comprising arsenic, phosphorus, and antimony applied with a dose of from about 1E15 cm^-2 to about 6E15 cm^- implanted at an energy of from about 30 KeV to about 80 KeV.

5. The method of claim 1 wherein subsequent to removing said spacer layer the step follows comprising,

said silicon dioxide layer comprises a gate oxide layer having a thickness between about 60 Å

and about 200 Å

said gate oxide layer being formed ever said device including said trenches.

6. The method of claim 5 wherein subsequent to forming said gate oxide layer over said device including said trenches the step follows comprising,

said source/drain annealing of said device to drive in said deposit of ion implanted dopant into said substrate to form source regions and drain regions therein is performed at a temperature from about 850°

C. to about 1,000°

C. for a time from about 20 minutes to about 90 minutes.

7. The method of claim 5 wherein source regions extend across beneath said trenches and said drain regions are juxtaposed with said trenches above the ends of said source regions.

8. The method of claim 1 wherein subsequent to forming and patterning said conductive word-line the steps are performed comprising

forming a code implant mask over said word-line layer, and

ion implanting through said code implant mask into said device.

9. A method of manufacture of a semiconductor memory device including a silicon semiconductor substrate with a vertical channel comprising the sequence of steps as follows:

forming a first dielectric masking layer patterned with pattern of trench openings therethrough on said substrate,

etching of trenches in the surface of the semiconductor substrate through said first dielectric masking layer,

said trenches having bases and sidewalls, said substrate having upper surfaces between and/or aside from said trenches,

removing said masking layer,

forming a spacer layer on the surface of said device,

shaping said spacer layer to form spacers ever said silicon substrate in said trenches along said sidewalls,

depositing a layer of a metal selected from the group consisting of W, Ti, Co, Me, and Ta ever said substrate including said trenches,

annealing said device to form silicides between said layer of metal and said silicon substrate,

etching away unreacted metal,

ion implanting source/drain dopant into said substrate,

annealing said device to activate said source/drain dopant to form source/drain regions in said silicon semiconductor substrate,

removing said spacers from said device,

formation of a gate oxide layer over said device, and

forming and patterning a conductive word-line ever said dielectric layer.

10. The method of claim 9 wherein said spacers are formed by the steps comprising

removing said masking silicon dioxide layer exposing said substrate including said trenches,

forming said spacer layer comprising silicon nitride over said said substrate including said trenches, and

etching said spacer layer to form said spacers.

11. The method of claim 9 wherein

said spacers are formed by the steps of:

a) first removing said masking silicon dioxide layer exposing said substrate including said trenches, and

b) second etching said spacer layer to form said spacers,

then subsequent to formation of said spacers the step follows comprising,

deposition of a metal on the surface of said device on top of said silicon substrate.

12. The method of claim 11 wherein said metal comprises cobalt.

13. The method of claim 11 wherein subsequent to deposition of said metal on the surface of said device the step follows comprising,

formation of a silicide from said doped surfaces of said substrate including the surfaces of said trenches with the exception of the surfaces protected by said spacers.

14. The method of claim 13 wherein subsequent to formation of said silicide the step follows comprising,

performing said source/drain self-aligned ion implantation.

15. The method of claim 14 wherein subsequent to said source/drain self-aligned ion implantation the step follows comprising,

removing said spacers, whereby said substrate including said trenches is exposed, and

annealing said device to drive in said deposit of ion implanted dopant into said substrate to form source regions and drain regions therein is performed at a temperature from about 750°

C. to about 900°

C. for a time of at least 20 minutes.

16. The method of claim 15 wherein subsequent to removing said spacers and annealing, the step follows comprising,

forming a gate oxide layer having a thickness between about 60 Å

and about 200 Å

, said gate oxide layer being formed over said device including said trenches.

17. The method of claim 16 wherein subsequent to forming a gate oxide layer over said device including said trenches the step follows comprises

formation of a gate word line layer over said gate oxide layer.

18. The method of claim 15 wherein source regions extend across beneath said trenches and said drain regions are juxtaposed with said trenches above the ends of said source regions.

19. The method of claim 9 wherein subsequent to forming and patterning said conductive word-line the steps are performed comprising

forming a code implant mask over said word-line layer, and

ion implanting through said code implant mask into said device.

20. The method of claim 9 including

removing said masking silicon dioxide layer to expose said substrate including said trenches by wet chemical etching using an etchant selected from the group consisting of hydrogen fluoride and buffered oxide etchant,

forming said spacers by the steps of:

a) depositing said spacer layer comprising silicon nitride having a thickness between about 1,500 Å and

about 4000 Å

deposited by LPCVD over said substrate including said trenches,

b) second etching said spacer layer to form said spacers,

then subsequent to formation of said spacers a subsequent step follows comprising,

deposition of cobalt metal on the surface of said device on top of said silicon substrate,

subsequent to deposition of said cobalt metal on the surface of said device the step follows comprising,

formation of cobalt silicide from said doped surfaces of said substrate including the surfaces of said trenches with the exception of the surfaces protected by said spacers,

subsequent to formation of said silicide the step follows comprising, performing said source/drain self-aligned ion implantation,

subsequent to said source/drain self-aligned ion implantation the step follows comprising,

removing said spacers, whereby said substrate including said trenches is exposed, and

annealing said device to drive in said deposit of ion implanted dopant into said substrate to form source regions and drain regions therein is performed at a temperature from about 750°

C. to about 900°

C. for a time of at least 20 minutes,

subsequent to removing said spacers and annealing, the step follows comprising,

forming a gate oxide layer having a thickness between about 60 Å and

about 200 Å

by a method selected from the group consisting of thermal oxidation and high temperature oxide deposition,

said gate oxide layer being formed over said device including said trenches,

subsequent to forming a gate oxide layer over said device including said trenches the step follows comprises formation of a gate word line layer over said gate oxide layer, and

said source regions extend across beneath said trenches and said drain regions are juxtaposed with said trenches above the ends of said source regions,

wherein subsequent to forming and patterning said conductive word-line the steps are performed comprising

forming a code implant mask over said word-line layer, and

ion implanting through said code implant mask into said device.

21. A method of manufacture of a semiconductor memory device on a silicon semiconductor substrate with a vertical channel comprising the sequence of steps as follows:

forming a silicon dioxide masking layer patterned with pattern of trench openings therethrough on said substrate,

etching of trenches in the surface of the semiconductor substrate through said silicon dioxide masking layer,

said trenches having bases and sidewalls, said substrate having upper surfaces between and/or aside from said trenches,

removing said masking layer,

forming a sub-spacer dielectric layer composed of silicon dioxide on the surface of said device,

forming a spacer layer composed of a material selected from the group consisting of polysilicon and silicon nitride over said sub-spacer dielectric layer,

shaping said spacer layer to form spacers in said trenches along said sidewalls,

ion implanting source/drain ions to deposit dopant in said substrate,

removing said spacers and said sub-spacer layer from said device,

forming a gate oxide layer over said device,

annealing said device to form source/drain regions in said silicon semiconductor substrate, and

forming and patterning a conductive word-line over said dielectric layer.

22. The method of claim 21 wherein

said trenches are formed by forming said first dielectric layer for masking comprising a silicon dioxide layer on said silicon substrate, and forming a photoresist mask on said masking silicon dioxide layer,

etching said masking silicon dioxide layer through said photoresist mask to form a trench mask in said masking silicon dioxide layer, and

etching of said silicon through said trench mask formed by said masking silicon dioxide layer to form said trench.

23. The method of claim 22 wherein said spacers are formed by the steps comprising

removing said masking silicon dioxide layer,

forming said sub-spacer dielectric layer of silicon dioxide having a thickness between about 200 Å

and about 1,000 Å

over said device including said trenches,

forming said spacer layer having a thickness between about 1,500 Å and

about 4,000 Å

over said sub-spacer dielectric layer, and

then etching said spacer layer by plasma etching to form said spacers.

24. The method of claims 21 wherein subsequent to removing said spacer layer and said sub-spacer layer the step follows comprising,

forming a gate oxide layer over said device including said trenches.

25. The method of claim 24 wherein subsequent to forming a gate oxide layer over said device including said trenches the step follows comprising,

source/drain annealing said device to drive in said deposit of ion implanted dopant into said substrate to form source regions and drain regions therein.

26. The method of claim 24 wherein source regions extend across beneath said trenches and said drain regions are juxtaposed with said trenches above the ends of said source regions.

27. The method of claim 21 wherein

said trenches are formed by forming said first dielectric layer for masking comprising a silicon dioxide layer on said silicon substrate, and forming a photoresist mask on said masking silicon dioxide layer,

etching said masking silicon dioxide layer through said photoresist mask to form a trench mask in said masking silicon dioxide layer, and

etching of said silicon through said trench mask formed by said masking silicon dioxide layer to form said trench,

removing said masking silicon dioxide layer,

forming said sub-spacer dielectric layer of silicon dioxide having a thickness between about 200 Å

and about 1,000 Å

over said device including said trenches,

forming said spacer layer having a thickness between about 1,500 Å and

about 4,000 Å

over said sub-spacer dielectric layer, and

then etching said spacer layer by plasma etching to form said spacers,

subsequent ion implanting source/drain ions to deposit dopant in said substrate and subsequent to removing said spacer layer and said sub-spacer layer the step follows of forming a gate oxide layer over said device including said trenches,

subsequent to forming said gate oxide layer over said device including said trenches the step follows comprising source/drain annealing said device to drive in said deposit of ion implanted dopant into said substrate to form therein source regions and drain regions in said substrate.

28. The method of claim 21 wherein subsequent to removing said spacer layer and said sub-spacer layer the step follows comprising,

said silicon dioxide layer comprises a gate oxide layer having a thickness between about 60 Å

and about 200 Å

, said gate oxide layer being formed over said device including said trenches.

29. The method of claim 21 wherein subsequent to forming said gate oxide layer over said device including said trenches the step follows comprising,

said source/drain annealing of said device to drive in said deposit of ion implanted dopant into said substrate to form source regions and drain regions therein is performed at a temperature from about 850°

C. to about 1,000°

C. for a time from about 20 minutes to about 90 minutes.

30. The method of claim 21 wherein subsequent to forming and patterning said conductive word-line the steps are performed comprising

forming a code implant mask over said word-line layer, and

ion implanting through said code implant mask into said device.

31. The method of claim 21 including

removing said masking silicon dioxide layer to expose said substrate including said trenches by wet chemical etching using an etchant selected from the group consisting of hydrogen fluoride and buffered oxide etchant,

forming said spacers by the steps of:

a) depositing said spacer layer comprising silicon nitride having a thickness between about 1,500 Å and

about 4000 Å

deposited by LPCVD over said substrate including said trenches,

b) second etching said spacer layer to form said spacers,

then subsequent to formation of said spacers a subsequent step follows comprising,

deposition of cobalt metal on the surface of said device on top of said silicon substrate,

subsequent to deposition of said cobalt metal on the surface of said device the step follows comprising,

formation of cobalt silicide from said doped surfaces of said substrate including the surfaces of said trenches with the exception of the surfaces protected by said spacers,

subsequent to formation of said silicide the step follows comprising, performing said source/drain self-aligned ion implantation,

subsequent to said source/drain self-aligned ion implantation the step follows comprising,

removing said spacers, whereby said substrate including said trenches is exposed, and

annealing said device to drive in said deposit of ion implanted dopant into said substrate to form source regions and drain regions therein is performed at a temperature from about 750°

C. to about 900°

C. for a time of at least 20 minutes,

subsequent to removing said spacers and annealing, the step follows comprising,

forming a gate oxide layer having a thickness between about 60 Å and

about 200 Å

by a method selected from the group consisting of thermal oxidation and high temperature oxide deposition,

said gate oxide layer being formed over said device including said trenches,

subsequent to forming a gate oxide layer over said device including said trenches the step follows comprises formation of a gate word line layer over said gate oxide layer, and

said source regions extend across beneath said trenches and said drain regions are juxtaposed with said trenches above the ends of said source regions,

wherein subsequent to forming and patterning said conductive word-line the steps are performed comprising,

forming a code implant mask over said word-line layer, and

ion implanting through said code implant mask into said device.