High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

• US 5,596,205 A
• Filed: 05/19/1995
• Issued: 01/21/1997
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Reedy, Ronald E.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/445,144
• Time in Patent Office: 613 Days
• Field of Search: 257/9, 257/327, 257/347, 257/352, 437/26, 437/84, 437/105, 437/248, 437/913
• US Class Current: 257/9
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS
• CPC Class Codes: Y10S 438/967 Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/974 Substrate surface preparation
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Claims

1. An analog electronic circuit having a substantially monotonic gain characteristic and negligible kink effect comprising:

an electrically insulating substrate;

a semiconductive silicon layer that is formed on the substrate and has a thickness of less than approximately 110 nanometers and an areal density of electrically active states less than approximately 5×

10¹¹ cm^-2 in regions which are not intentionally doped; and

an analog field effect transistor element that is formed in the silicon layer and has a gate length of less than approximately 0.8 micrometers.

2. A circuit as in claim 1 in which the transistor element is configured as a transmission gate.

3. A circuit as in claim 1 in which the transistor element comprises a gate insulating layer having a thickness that is selected to limit offset voltage variations due to active states of less than approximately three millivolts.

4. A circuit as in claim 1 wherein said electrically insulating substrate further comprises sapphire.

5. An analog electronic circuit having a substantially monotonic gain characteristic and negligible kink effect comprising:

an insulating substrate;

a silicon layer formed on said insulating substrate wherein said silicon layer is less than approximately 1000 Å

thick and is substantially free of electrically active states achieved by restricting all processing of said silicon layer to temperatures of less than or equal to approximately 950°

C.; and

an analog field effect transistor element that is formed in said silicon layer and has a gate length of less than approximately 0.8 micrometers.

6. An analog electronic circuit as defined in claim 5 wherein said insulating substrate comprises sapphire.

7. An analog electronic circuit as defined in claim 5 wherein said silicon layer has an areal density of electrically active states in regions which are not intentionally doped which is less than approximately 5×

10¹¹ cm^-2.

8. An analog electronic circuit as defined in claim 5 wherein said analog field effect transistor element is configured as a transmission gate.

9. An analog electronic circuit as defined in claim 5 wherein said analog field effect transistor element further comprises a gate insulating layer having a thickness that is selected to limit offset voltage variations due to active states of less than approximately three millivolts.

10. An analog electronic circuit which includes an analog field effect transistor element that is formed in a silicon layer on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2, said analog electronic circuit produced by the process comprising the steps of;

epitaxially depositing said silicon layer on a surface of said sapphire substrate;

implanting a given ion species into said silicon layer under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said silicon layer, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;

maintaining said silicon layer at or below a predetermined temperature which is substantially uniform throughout said silicon layer during said ion implanting step;

annealing said silicon layer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and

performing all annealing and processing procedures at or below a temperature of approximately 950°

C. thereby maintaining an areal density of electrically active states in regions of said silicon layer not intentionally doped which is less than approximately 5×

10¹¹ cm^-2.

11. An analog electronic circuit produced by the process defined in claim 10 wherein said step of maintaining said silicon layer at or below a predetermined temperature further includes selecting said predetermined temperature to be approximately zero degrees centigrade (0°

C.).