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Non-volatile memory system of multi-level transistor cells and methods using same

  • US 5,596,526 A
  • Filed: 08/15/1995
  • Issued: 01/21/1997
  • Est. Priority Date: 08/15/1995
  • Status: Expired due to Term
First Claim
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1. A memory array of multi-level non-volatile single transistor cells, wherein each cell is configured to store more that a single data bit, the array comprising:

  • a plurality of groups, each group comprising a plurality of memory cells, each memory cell having a control gate, a floating gate and a channel formed between a source and a drain, wherein the memory cells for each of the groups are coupled with their respective channels in series;

    a plurality of select transistors, wherein two of the select transistors are coupled for selecting each group;

    a programming circuit for selectively programming each of the memory cells to a predetermined current level in accordance with one of N gate voltages by storing a predetermined charge onto each of the respective floating gates wherein each of the N threshold voltages is representative of a predetermined collection of data bits;

    a plurality of N write reference cells, N write reference cells for each memory cell in a group, each of the N write reference cells corresponding to the N predetermined reference voltages; and

    a circuit for sequentially comparing a current through one of the memory cells to a current through each of the appropriate N write reference cells for storing a collection of data bits.

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