Non-volatile memory system of multi-level transistor cells and methods using same

• US 5,596,526 A
• Filed: 08/15/1995
• Issued: 01/21/1997
• Est. Priority Date: 08/15/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Microsystems Incorporated (Micron Technology, Inc.)
• Inventors: Keshtbod, Parviz, Assar, Mahmud
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US08/515,188
• Time in Patent Office: 525 Days
• Field of Search: 365/184, 365/104, 365/185.03, 365/185.17, 365/185.24
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output

Abstract

A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.

Claims

1. A memory array of multi-level non-volatile single transistor cells, wherein each cell is configured to store more that a single data bit, the array comprising:

a plurality of groups, each group comprising a plurality of memory cells, each memory cell having a control gate, a floating gate and a channel formed between a source and a drain, wherein the memory cells for each of the groups are coupled with their respective channels in series;

a plurality of select transistors, wherein two of the select transistors are coupled for selecting each group;

a programming circuit for selectively programming each of the memory cells to a predetermined current level in accordance with one of N gate voltages by storing a predetermined charge onto each of the respective floating gates wherein each of the N threshold voltages is representative of a predetermined collection of data bits;

a plurality of N write reference cells, N write reference cells for each memory cell in a group, each of the N write reference cells corresponding to the N predetermined reference voltages; and

a circuit for sequentially comparing a current through one of the memory cells to a current through each of the appropriate N write reference cells for storing a collection of data bits.

2. The memory array according to claim 1 further comprising:

(a) a plurality of N read reference cells, N read reference cells for each memory cell in a group, each of the N read reference cells corresponding to the N predetermined reference voltages; and

(b) a circuit for sequentially comparing a current through one of the memory cells to a current through each of the appropriate N read reference cells for determining a stored collection of data bits.

3. The memory array according to claim 1 wherein said circuit for sequentially comparing is further coupled to logic for disabling further programming of memory cells being programmed upon completion of programming of the same.

4. The memory array according to claim 2 further comprising a comparator having a first input coupled to said N read reference cells through a read column select logic and a second input for providing a predetermined read current reference during programming of said read reference cells.

5. The memory array according to claim 4 wherein said comparator is comprised of a sense amplifier.

6. The memory array according to claim 1 further comprising a comparator having a first input coupled to said N write reference cells through a write column select logic and a second input selectively coupled to either receive a predetermined write current reference during programming of said write reference cells or one of said N read reference cells during reading of said memory cells.

7. The memory array according to claim 6 wherein said comparator is comprised of a sense amplifier.

8. The memory array according to claim 1 further comprising address decode having row select logic coupled to said memory cells, read reference cells and write reference cells and further having column select logic coupled to said memory cells for selecting a memory cell for programming or reading wherein the selected cell is kept in saturation mode during reading of the same while remaining cells are maintained in linear mode.

9. The memory array according to claim 8 further comprising comparator circuitry having a first input coupled to said memory cells for receiving the current through a selected memory cell and a second input selectively coupled to receive the current through either one of said corresponding N read reference cells during a memory read operation or the current through one of said corresponding N write reference cells during a memory write operation.

10. The memory array according to claim 8 further comprising a counter coupled to said read and write column select logics for sequentially providing N logic states, each state representing one of said N reference voltages wherein said counter starts counting from logic state O and increments through to logic state N during programming of each of said memory, read and write reference cells and starts from logic state N and decrements through to logic state O during reading of the same.

11. The memory array according to claim 10 further comprising means coupled to an I/O bus for comparing during a memory, read reference, and write reference program operations a binary value to be programmed into a selected memory cell to the logic state provided by said counter and upon successful comparison thereof providing an output for disabling further programming of said selected memory cell.

12. The memory array according to claim 11 further comprising a storage device coupled between said I/O bus and said counter.

18. The method according to claim 1 wherein during said memory cell programming step, applying 4 reference voltages (N=4), each reference voltage representative of data bits `00`, `01`, `10`, and `11` respectively by first applying one of the reference voltages representative of data bits `00` to all of the memory cells being programmed, then applying the reference voltage representative of data bits `01` to all memory cells except the ones already programmed, further applying the reference voltage representative of data bits `10` to all memory cells except the ones already programmed, finally applying the reference voltage representative of data bits `11` to those memory cells selected to be programmed to logic state `11`.

13. A method of programming a memory array of multi-level non-volatile single transistor cells, wherein each cell is configured to store more than a single data bit, the method comprising the steps of:

providing a plurality of groups, each group comprising a select transistor and a plurality of memory cells, each memory cell having a control gate, a floating gate and a channel formed between a source and a drain, wherein the memory cells for each of the groups are coupled with their respective channels in series;

selectively programming each of the memory cells to a predetermined current level by applying one of N gate voltages by storing a predetermined charge onto each of the respective floating gates wherein each of the N threshold voltages is representative of a predetermined collection of data bits;

reading the memory tells by sequentially comparing a current through the memory cells to a current through one each of said N read reference cell for determining a stored collection of data bits; and

gauging reading time of the memory cells by reading one each of N corresponding write and read reference cells simultaneously with said reading of a corresponding memory cell thereby providing sufficient memory cell reading time.

14. The method according to claim 13 further comprising the step of programming each of said N read reference cells to a predetermined reference current level during system initialization.

15. The method according to claim 14 further comprising the step of programming each of said N write reference cells to a predetermined reference current level being lower than the read reference current level during system initialization.

16. The method according to claim 13 further comprising the step of maintaining transistors of the selected memory cells during said programming step 5(b) in saturation mode while maintaining transistors of remaining unselected memory cells of the plurality of groups of cells in linear mode.

17. The method according to claim 13 further comprising the step of programming the memory cells by sequentially comparing a current through one of the memory cells to a current through one of corresponding N write reference cell for writing a stored collection of data bits to the memory cells.

19. The method according to claim 17 further comprising the step of after completion of programming of a selected cell to the reference voltage representative of the desired data bit state, disabling further programming of the same until after said plurality of groups of cells have been erased.

20. A multi-level non-volatile memory system comprising:

(a) a memory array comprised of a plurality of memory blocks;

(b) a plurality of read reference blocks;

(c) a plurality of write reference blocks; and

(d) a circuit utilizing said read and write reference blocks to program and read a select group of said memory cells wherein one of N gate voltages representing a predetermined binary value is applied to the memory cell of said select group of cells until a predetermined current is reached,

wherein each of said memory, read reference and write reference blocks having at least one row and one column of single transistor cells, each of said column of cells arranged in NAND type architecture having two select transistors and each of said cells having a floating gate for storing more than a single data bit of information within each cell.

21. A multi-level non-volatile memory system according to claim 20 further comprising address decode having row select logic coupled to said memory cells, read reference cells and write reference cells and further having column select logic coupled to said memory cells for selecting a memory cell for programming or reading wherein the selected cell is kept in saturation mode during reading of the same while remaining cells are maintained in linear mode.

22. A multi-level non-volatile memory system according to claim 20 further comprising column select logic coupled to said read reference blocks for selecting a column of read reference cells and further having column select logic coupled to said write reference blocks for selecting a column of write reference cells.

23. A multi-level non-volatile memory system according to claim 20 further comprising a counter coupled to said read and write column select logics for sequentially providing N logic states, each state representing one of said N reference voltages starting with logic state O and incrementing through to logic state N during programming of each of said memory, read and write reference cells and starting from logic state N and decrementing through to logic state O during reading of each of said memory, read and write reference cells.

24. A multi-level memory system according to claim 23 further comprising means coupled to an I/O bus for comparing during a memory programming operation a binary value to be programmed into a selected memory cell to the logic state provided by said counter and upon successful comparison thereof providing an output for disabling further programming of said selected memory cell.

25. A multi-level memory system according to claim 24 further comprising a storage means coupled between said I/O bus and said comparing means.

26. A multi-level non-volatile memory system according to claim 20 further comprising comparator circuitry having a first input coupled to said memory cells for receiving the current through a selected memory cell and a second input selectively coupled to receive the current through either a read reference cell corresponding to said selected memory cell during a memory read operation or the current through a write reference cell corresponding to said selected memory cells during a memory write operation.

27. A multi-level non-volatile memory system according to claims 21 or 22 further comprising a read reference comparator having a first input coupled to said read column select and a second input coupled to receive a predetermined current reference level for comparing said first and second inputs when verifying programming said read reference blocks during system initialization.

28. A multi-level non-volatile memory system according to claims 21 or 22 further comprising a write reference comparator having a first input coupled to said write column select and a second input selectively coupled to receive a predetermined current reference level when verifying programming said write reference blocks during system initialization or coupled to said read column select during reading of said memory array.