Method of using source bias to raise threshold voltages and/or to compact threshold voltages

• US 5,596,528 A
• Filed: 09/22/1995
• Issued: 01/21/1997
• Est. Priority Date: 10/04/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kaya, Cetin, Mezenner, Rabah, Holland, Wayland B.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Tran, Andrew Q.
• Application Number:
  US08/532,313
• Time in Patent Office: 487 Days
• Field of Search: 365/185.24, 365/185.02, 365/185.12, 365/185.18, 365/185.27, 365/185.3, 365/185.33
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits

Abstract

The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.

Claims

1. A method for increasing the thresttold voltage of at least one of a plurality of floating-gate memory cells in a nonvolatile integrated-circuit memory having a substrate connected to a reference voltage, each said memory cell being of the single-transistor, non-slit-gate type, said method comprising:

connecting the sources of said plurality of memory cells to a high impedance;

causing currents to flow into the drains of said plurality memory cells; and

placing a voltage on the control gates of said plurality of memory cells, said voltage being positive with respect to said reference voltage.

2. The method of claim 1, wherein a field-effect transistor in an "OFF" state is used to attain said high impedance.

3. The method of claim 1, wherein said plurality of memory cells is 10,000 of said memory cells, wherein a current of 100 microamperes is caused to flow into the parallel-connected drains of said plurality of memory cells and wherein said voltage on the control gates of said plurality memory cells is +5 volts with respect to said reference voltage, both for a period of one second.

4. The method of claim 1, wherein said plurality of memory cells is a column of memory cells.

5. The method of claim 1, said memory further having a ground voltage, wherein said reference voltage is said ground voltage.