Device for wireless transmission of digital data, in particular of audio data, by infrared light in headphones

• US 5,596,603 A
• Filed: 08/22/1994
• Issued: 01/21/1997
• Est. Priority Date: 08/23/1993
• Status: Expired due to Fees

• Current Assignee: Sennheiser Electronic GmbH & Company KG
• Original Assignee: Sennheiser Electronic GmbH & Company KG
• Inventors: Delibruegge, Karl-Hermann, Haupt, Axel
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): NGUYEN, THUY LIEU T
• Application Number:
  US08/293,972
• Time in Patent Office: 883 Days
• Field of Search: 375/242, 375/253, 375/246, 375/359, 341/55, 370/82, 370/83, 370/84, 370/53, 370/69.1, 370/77, 371/42, 371/37.1, 371/46, 371/8.2
• US Class Current: 375/242
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H04B 10/114 Indoor or close-range type systems
• CPC Class Codes: H04L 25/4908 using mBnB codes
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit
• CPC Class Codes: H04S 1/007 in which the audio signals are in digital form data reduction aspects thereof based on psychoacoustics G10L19/02

Abstract

Infrared light is used in a device for wireless transmission of digital data, e.g. in headphones. In order to satisfy the strict requirements regarding compactness and power consumption, it is proposed that three digital stereo sampling values are encoded in data frames of 128-bit length for channel coding. Control characteristics and synchronizing characteristics are added to these data frames. A special coding rule is used for the sampling value coding.

Claims

1. A process for the wireless transmission of digital audio data, comprising the steps of:

based on digital stereo sampling values (audio data

     3) having a word length of 16 bits in each instance and based on a system clock rate of 256-times the sampling rate (transmitter base clock

     1), forming a data frame having a bit length of 128 bits for the transmission data (9, 20,

     47), wherein the data frame contains three stereo sampling values (3) at the sampling rates of 48 kHz (A) and 44.1 kHz (B) or two stereo sampling values (3) at the sampling rate of 32 kHz (C) and, instead of the third stereo sampling value (3), contains a filling pattern and coded information about the current sampling rate;

sending the transmission data (9, 20,

     47) at a transmission data rate which is obtained from the transmission base clock (1) by integral division;

feeding the transmission data (9, 20,

     47) after transmission to a receiver parallel to a decoding device (24, 25,

     26) and to a clock pulse recovery (21);

regenerating a clock pulse (22,

     45) which is an integral multiple of (N-times) the transmission data rate by the clock pulse recovery (21); and

deriving by integral division the clock pulses required for a channel decoder (block decoder

     25) for decoding the data stream of the data frames of 128-bit length, by a receiver base clock (22) and the transmitter base clock (1) which is 256-times the sampling rate.

2. The process according to claim 1, wherein the transmission data rate is obtained from the transmitter base clock (1) by dividing by 6 at sampling rates of 48 kHz (A) and 44.1 kHz (B) or by dividing by 4 at the sampling rate of 32 kHz (C).

3. The process according to claim 1, wherein the clock (2, 45) regenerated in the clock pulse recovery (21) is 12-times the transmission data rate (N=12).

4. The process according to claim 1, wherein the audio data (3) and the filling pattern, if any, are provided with a code conversion from 4 bits to 5 bits, specifically with a code which generates a frequent level change in the data stream, wherein code words which generate frequent level changes especially when repeated are used in allocating for the code conversion to 5-bit code words in bit groups which occur frequently in digital audio signals.

5. The process according to claim 4, wherein during code conversion the 5-bit code words corresponding to the 4-bit data are allocated in accordance with the code in the following coding table:

space="preserve" listing-type="tabular">______________________________________ 4-bit blocks of recoded 5-bit audio data (3) blocks ______________________________________ 0000 01010 0001 10100 0010 11010 0011 01001 0100 10010 0101 10111 0110 11101 0111 11110 1000 01110 1001 11001 1010 01111 1011 11011 1100 10110 1101 01101 1110 10101 1111 01011 ______________________________________

6. The process according to claim 4, wherein a 5-bit group which does not occur in the code for conversion of the audio data (3) and filling pattern, if any, is placed at the beginning of the data frame as a preamble (8) in a register of the coding device (63) as synchronization characteristic for detecting the start of the frame in the decoding device (68).

7. The process according to claim 4, wherein the transmission data (9, 20, 47) arriving at the receiver are checked in a preamble detector (27) to determine whether or not they have, at the starting position, the 5-bit group which was selected as a preamble and, if this preamble is present, the original digital audio data (3) which are then converted in the block coder (5) or in the coding device (63) are reproduced therefrom in the block decoder (25) in 4-bit groups corresponding to the conversion code.

8. The process according to claim 1, wherein an infrared light which is timed with the transmission data (9, 20, 47) is used as transmission medium.

9. The process according to claim 1, wherein the transmission data (9, 20, 47) are first modulated to a high-frequency carrier and are then transmitted by infrared light.

10. The process according to claim 1, wherein a HF carrier which is timed with the transmission data (9, 20, 47) is used as transmission medium.

11. The process according to claim 16, wherein the transmission data (9, 20, 47) are modulated to a HF carrier.

12. A device for carrying out a process for the wireless transmission of digital audio data, comprising the steps of, based on digital stereo sampling values (audio data 3) having a word length of 16 bits in each instance and based on a system clock rate of 256-times the sampling rate (transmitter base clock 1), forming a data frame having a bit length of 128 bits for the transmission data (9, 20, 47), wherein the data frame contains three stereo sampling values (3) at the sampling rates of 48 kHz (A) and 44.1 kHz (B) or two stereo sampling values (3) at the sampling rate of 32 kHz (C) and, instead of the third stereo sampling value (3), contains a filling pattern and coded information about the current sampling rate, sending the transmission data (9, 20, 47) at a transmission data rate which is obtained from the transmission base clock (1) by integral division, feeding the transmission data (9, 20, 47) after transmission to a receiver parallel to a decoding device (24, 25, 26) and to a clock pulse recovery (21), regenerating a clock pulse (22, 45) which is an integral multiple of (N-times) the transmission data rate by the clock pulse recovery (21), and deriving by integral division the clock pulses required for a channel decoder (block decoder 25) for decoding the data stream of the data frames of 128-bit length, by a receiver base clock (22) and the transmitter base clock (1) which is 256-times the sampling rate,

with channel coding taking place in a coding device (63) and based upon a transmitter base clock (1) and with decoding talking place in a decoding device (68), said device comprising that:

said decoding device (68), for the purpose of clock pulse recovery (21) containing a phase control loop (PLL 40, 42, 44,

     46) with a flank detector (46) for signaling the change in level, a filter (42), and a voltage-controlled oscillator (VCO

     44);

said phase control loop (PLL 40, 42, 44,

     46) containing a state machine (40) which operates in frequency-selective mode as well as in phase-selective mode as a frequency comparator and phase comparator for clock pulse recovery and multiplication by the factor N;

said state machine (40) being coupled on an input side with said flank detector (46) and voltage-controlled oscillator (44) and on an output side with said filter (42); and

said state machine (40) remaining in a basic state of a first, frequency-selective work cycle with a quantity of possible recurring states until the incoming data stream has a change in level, is then switched farther at every clock pulse by one state in this first work cycle and, when no further change in level occurs, returns to the basic state of this first work cycle after passing through the quantity of possible repeating states, but passes into the state following the basic state when a change in level occurs and, in so doing, transmits a positive control pulse (41) to the filter (42) if less than N clock pulses have occurred since the last change in level, or transmits a negative control pulse (41) to the filter (42) if more than N clock pulses have occurred since the last change in level, or, finally, jumps to a second, phase-selective work cycle with N possible repeating states if exactly N clock pulsers have occurred since the last change in level; and

said state machine being then switched farther at every clock pulse by one state in the second work cycle, wherein a negative control pulse (41) is sent to the filter (42) whenever a change in level occurs in the region between the state (16) before the jumping point (17) until the state N/4 (third state 20, where N=12,

     20) after the jumping point (17), or a positive control pulse (41) is sent to the filter (42) whenever a change in level occurs in the region between the state N/2 (sixth state 23, where N=12) after the jumping point (17) until the state 5/6 N (tenth state 27, where N=12) after the jumping point (17), or jumps back into the basic state (0) of the first work cycle without initiating a control pulse (41 ) when a change in level occurs in the region between the state N/3 (fourth state 21, where N=12) and state 5/12 N, (fifth state 22, where N=12) after the jumping point (17), i.e., when there is an excessive divergence in frequency between the Nth of the receiver basic clock (22,

     45) and the transmission data rate. (FIGS. 4, 5 and

     6).

13. The device according to claim 12, wherein an interface decoder (61), which has a signal feed (60) in accordance with DIN EN 60958, serves as a source for the system clock (I) and the digital audio data (3).