Method and apparatus for programming embedded memories of a variety of integrated circuits using the IEEE test access port
First Claim
1. In an integrated circuit having processor means for processing instructions, storage means comprising one of an embedded memory and an on-chip cache and a memory unit having a memory bus coupled to the storage means for enabling access to the storage means, an apparatus is provided for programming memory locations of the storage means, the apparatus comprising:
- a shift register disposed within the integrated circuit having a command field, an address field and a data field;
an input/output means disposed within the integrated circuit and coupled between an external system outside of the integrated circuit and the shift register for transmission of signals comprising an instruction specifying a write command, an address specifying a memory location within the storage means and data between the external system and the command field, the address field and the data field of the shift register, respectively;
first, second and third registers disposed within the memory unit and being coupled to the shift register for receiving from the command field, address field and data field of the shift register the instruction, address and data, respectively;
executable cede stored within the storage means for executing the instruction stored within the first register and writing the data stored in the third register to the memory location specified by the address stored in the second register; and
an interrupt unit coupled to the first register of the memory unit and to the processor means of the integrated circuit for interrupting operation of the processor means upon receipt of the instruction by the first register and transferring processor control to the executable code stored in the storage means.
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Abstract
The present invention provides a method and apparatus for programming embedded memories or on-chip caches of a variety of integrated circuits through use of the IEEE Test Access Port (TAP) architecture and logic. To accomplish this, the TAP architecture is utilized to serially shift address, data and command information into respective register chains of a RISM ACTION register located within a memory interface unit of the integrated circuit. The TAP architecture includes, among other things, a TAP port, a TAP controller and an instruction register. According to the general method used to program the embedded memories, the external system transmits a plurality of sequential signals to respective register chains of the RISM ACTION register, each sequential signal comprising an instruction specifying a write command, an address specifying a consecutive memory location within the storage means and consecutive data strings to be written to the consecutive memory locations. Next, the instruction, address and data input to the RISM ACTION register chains are transmitted in parallel to corresponding first, second and third core registers disposed within a memory unit of the integrated circuit. Upon receipt of the instruction in the first core register, an interrupt unit interrupts operation of the integrated circuit'"'"'s processor and transfers processor control to executable code stored in the storage means. The executable code then writes the data stored in the third core register to the memory location specified by the address stored in the second core register in response to execution of the instruction stored in the first register.
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Citations
10 Claims
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1. In an integrated circuit having processor means for processing instructions, storage means comprising one of an embedded memory and an on-chip cache and a memory unit having a memory bus coupled to the storage means for enabling access to the storage means, an apparatus is provided for programming memory locations of the storage means, the apparatus comprising:
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a shift register disposed within the integrated circuit having a command field, an address field and a data field; an input/output means disposed within the integrated circuit and coupled between an external system outside of the integrated circuit and the shift register for transmission of signals comprising an instruction specifying a write command, an address specifying a memory location within the storage means and data between the external system and the command field, the address field and the data field of the shift register, respectively; first, second and third registers disposed within the memory unit and being coupled to the shift register for receiving from the command field, address field and data field of the shift register the instruction, address and data, respectively; executable cede stored within the storage means for executing the instruction stored within the first register and writing the data stored in the third register to the memory location specified by the address stored in the second register; and an interrupt unit coupled to the first register of the memory unit and to the processor means of the integrated circuit for interrupting operation of the processor means upon receipt of the instruction by the first register and transferring processor control to the executable code stored in the storage means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. In an integrated circuit having processor means for processing instructions, a storage means comprising one of an embedded memory and an on-chip cache and a memory unit having a memory bus coupled to the storage means for enabling access to the storage means, a method is provided for programming memory locations of the storage means with input provided by an external system, the method comprising the steps of:
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A) transmitting as a first input from the external system to a shift register disposed within the integrated circuit a signal comprising instruction specifying a write command, an address specifying a memory location within the storage means and data, the shift register having a command field, an address field and a data field for storing the instruction, the address and the data transmitted from the external system, respectively; B) transmitting from the command, address and data fields of the shift;
register to first, second and third registers disposed within the memory unit of the integrated circuit the instruction, the address and the data, respectively;C) transferring processor control from the processor means to executable code stored in the storage means; D) writing the data stored in the third register to the memory location specified by the address stored in the second register in response to execution of the instruction stored in the first register by the executable cede; and E) repeating steps A), B) and D) until programming of the storage means is complete.
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10. In an integrated circuit comprising processor means for processing instructions, a storage means comprising one of an embedded memory and an on-chip cache and a memory unit having a memory bus coupled to the storage means for enabling access to the storage means, a method is provided for programming the storage means of the integrated circuit with input provided by an external system, the integrated circuit having an input/output (I/O) means for transmit flag signals between the external system and the integrated circuit, the I/O means comprising an input register coupled to the external system for receiving the input to the integrated circuit from the external system, an output connection for coupling output from the integrated circuit to the external system and an I/O controller coupled to the input register and the external system for controlling operation of the input register in response to the input to the integrated circuit from the external system, the method comprising the steps of:
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A) transmitting as a first serial input an operation code from the external system to the input register; B) transmitting in parallel the operation code from the input register to the I/O controller, the I/O controller requesting the memory bus in response to execution of the operation code; C) transmitting from the external system via the input register to a shift register within the integrated circuit a second serial input comprising an instruction specifying a write command, an address specifying a memory location within the storage means and data, the shift register comprising an instruction field, an address field and a data field and being serially coupled between the input register and the output connection for transmitting and receiving signals to and from the I/0 means, the command, address and data fields of the shift register coupled in parallel to corresponding first, second and third registers of the memory unit for reading and writing memory locations of the storage means; D) transmitting in parallel from the command, address and data fields of the shift register to the first, second and third registers of the memory unit the instruction, the address and the data, respectively; E) interrupting operation of the processor means upon receipt of the instruction, address and data in the first, second and third registers; F) transferring processor control from the processor means to executable code stored in the storage means; G) writing the data stored in the third register to the memory location specified by the address stored in the second register in response to execution of the instruction stored in the first register; and H) repeating steps C), D) and G) until programming of the storage means is complete.
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Specification