Mechanism for using common code to handle hardware interrupts in multiple processor modes

• US 5,596,755 A
• Filed: 05/08/1995
• Issued: 01/21/1997
• Est. Priority Date: 11/03/1992
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Lipe, Ralph A., Pletcher, Richard A.
• Primary Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US08/436,085
• Time in Patent Office: 624 Days
• Field of Search: 395/733, 395/734, 395/700, 395/416, 395/550, 395/406, 395/650
• US Class Current: 710/261
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

An interrupt handler may be run in multiple processor modes on a data processing system having a processor for executing instructions and a memory for storing information. The sharing of interrupt handler code across multiple processor modes minimizes the switching between processor modes during the handling of interrupts. The mode in which the interrupt handler executes is dictated by the current processor mode. The indicator of the current processor mode directs the interrupt handler to use information that is appropriate for the current processor mode.

Claims

1. In a data processing system having a processor for executing instructions and operating in different processor modes, a storage for storing information and an interrupt handler for handling a type of interrupt, a method of handling interrupts comprising the steps of:

a) storing an indicator of a current processor mode in the storage;

b) storing information to be used by the interrupt handler when run in a first processor mode in the storage and storing information to be used by the interrupt handler when run in a second processor mode in the storage;

c) receiving an interrupt of the type handled by the interrupt handler responds;

d) in response to receiving the interrupt, determining what the current processor mode is by examining the indicator in storage;

e) running the interrupt handler using the stored information for the first processor mode in response to determining that the current processor mode is the first mode to avoid switching processor modes; and

f) running the interrupt handler using the stored information for the second processor mode in response to determining that the current processor mode is the second processor mode to avoid switching processor modes.

2. A method as recited in claim 1, wherein the step of storing information to be used by the interrupt handler when run in the first processor mode comprises the step of storing information to be used by the interrupt handler when run in the first processor mode in which the instructions that are executed by the processor use virtual addresses.

3. A method as recited in claim 2 wherein the step of storing information to be used by the interrupt handler when run in the second processor mode comprises the step of storing information to be used by the interrupt handler when run in the second processor mode in which the instructions that are executed by the processor use physical addresses.

4. A method as recited in claim 2 wherein the step of storing information to be used by the interrupt handler when run in the first processor mode comprises the step of storing values that specify segments of memory in a virtual memory address space to be used by the interrupt handler when run in the first processor mode.

5. A method as recited in claim 4 wherein the step of storing values that specify segments of memory in a virtual address space comprises the step of storing at least one index to an entry in a segment descriptor table.

6. A method as recited in claim 1 wherein the step of storing information to be used by the interrupt handler when run in the first processor mode comprises the step of storing in the storage information to be used by the interrupt handler when run in the first processor mode in which the instructions that are executed by the processor use physical addresses.

7. A method as recited in claim 6 wherein the step of storing information to be used by the interrupt handler when run in the first processor mode in the storage comprises the step of storing values that specify memory blocks in a physical address space.

8. A method as recited in claim 1 wherein the step of storing information to be used by the interrupt handler when run in the first processor mode comprises the step of storing the information to be used by the interrupt handler when run in the first processor mode at a location in the storage that is offset by a fixed offset from a location that stores the information to be used by the interrupt handler when run in the second processor mode that is stored in the storage.

9. A method as recited in claim 8 wherein the step of storing the information to be used by the interrupt handler when run in the first processor mode comprises the step of storing the information to be used by the interrupt handler at a location in the storage that is offset by a fixed offset specified by the indicator of the current processor mode.

10. A method as recited in claim 9 wherein the step of storing the indicator of the current processor mode in the storage comprises the step of storing the fixed offset between the location in the storage that stores the information to be used by the interrupt handler when run in the first processor mode and the location in the storage that stores the information to be used by interrupt handler when run in the second processor mode as the indicator of the current processor mode.

11. A method as recited in claim 1 wherein the storage comprises a memory that is logically partitioned into segments of contiguous blocks of memory.

12. A method as recited in claim 11 wherein the first processor mode is a first privilege level, the second processor mode is a second privilege level, and privilege levels are associated with each segment of memory such that in order for the processor to gain access to a segment of memory, the processor must be executing in a processor mode having a privilege level that is equal or greater than the privilege level of the memory segment and wherein the step of storing information comprises the step of storing information to be used by the interrupt handler when run in the first privilege level and storing information to be used by the interrupt handler when run in the second privilege level.

13. A method as recited in claim 11 further comprising the steps of:

storing a control procedure for the first processor mode in the storage;

storing a control procedure for the second processor mode in the storage;

calling the control procedure of the first processor mode when the current processor mode is the first processor mode; and

calling the control procedure of the second processor mode when the current processor mode is the second processor mode.