Sub-bus activity detection technique for power management within a computer system
First Claim
1. A computer system comprising:
- a peripheral bus including a plurality of multiplexed address/data lines;
a latch having an input port coupled to said plurality of multiplexed address/data lines;
a data buffer having a first port coupled to said plurality of multiplexed address/data lines;
an integrated processor including;
a CPU core;
a local bus coupled to said CPU core;
a bus interface unit capable of interfacing data, address, and control signals between said local bus and said peripheral bus; and
a sub-bus control unit coupled to said bus interface unit and to said latch and capable of generating a loading signal indicative of the presence of a valid address on said peripheral bus;
a peripheral device having a plurality of addressing lines coupled to an output port of said latch, and a plurality of data lines coupled to a second port of said data buffer; and
a power management unit coupled to said peripheral bus including;
a power management state machine for managing power within said computer system;
a system monitor coupled to said power management state machine and to said peripheral bus; and
a configuration register coupled to said system monitor, wherein said power management unit is configured to use a value stored within said configuration register to control a period of time after an occurrence of an address phase of said peripheral bus at which data from said peripheral bus is shadowed within said power management unit and wherein said power management unit is configured to provide said shadowed data to said peripheral bus.
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Accused Products
Abstract
The computer system includes an integrated processor coupled to a power management unit and at least one peripheral device. The integrated processor includes a bus interface unit that provides an interface to a high performance peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals. Separate address and data lines from the integrated processor for the secondary bus are not required. Accordingly, high performance peripheral devices are supported by the integrated processor as well as lower performance, lower-cost peripherals without a significant increase in the pin-count of the integrated processor.
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Citations
13 Claims
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1. A computer system comprising:
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a peripheral bus including a plurality of multiplexed address/data lines; a latch having an input port coupled to said plurality of multiplexed address/data lines; a data buffer having a first port coupled to said plurality of multiplexed address/data lines; an integrated processor including; a CPU core; a local bus coupled to said CPU core; a bus interface unit capable of interfacing data, address, and control signals between said local bus and said peripheral bus; and a sub-bus control unit coupled to said bus interface unit and to said latch and capable of generating a loading signal indicative of the presence of a valid address on said peripheral bus; a peripheral device having a plurality of addressing lines coupled to an output port of said latch, and a plurality of data lines coupled to a second port of said data buffer; and a power management unit coupled to said peripheral bus including; a power management state machine for managing power within said computer system; a system monitor coupled to said power management state machine and to said peripheral bus; and a configuration register coupled to said system monitor, wherein said power management unit is configured to use a value stored within said configuration register to control a period of time after an occurrence of an address phase of said peripheral bus at which data from said peripheral bus is shadowed within said power management unit and wherein said power management unit is configured to provide said shadowed data to said peripheral bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification