High-yield spatial light modulator with light blocking layer

• US 5,597,736 A
• Filed: 06/07/1995
• Issued: 01/28/1997
• Est. Priority Date: 08/11/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sampsell, Jeffrey B.
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/482,598
• Time in Patent Office: 601 Days
• Field of Search: 437/180, 437/3, 437/4, 437/5, 437/2, 257/347
• US Class Current: 438/22
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 2203/12 spatial light modulator
• CPC Class Codes: G09F 9/372 the positions of the elements being controlled by the application of an electric field
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device with an optically active region which receives light, and has a layer of metal which blocks the light from the substrate. The substrate contains addressing circuitry which can experience current leakage if photocarriers are allowed to form by contact with light. A layer of metal is deposited as an integral part of the device to prevent the light from reaching the substrate.

Claims

1. A method of manufacturing a semiconductor device comprising:

a. preparing a substrate;

b. forming electrically active regions in said substrate;

c. depositing a blocking layer over said substrate;

d. depositing an electrode layer over said blocking layer; and

e. patterning said electrode layer to form landing and address electrodes separated by a gap, wherein said gap and said blocking layer are aligned such that light incident said semiconductor device which passes through said gap is blocked by said blocking layer.

2. The method of claim 1 wherein said forming step further comprises forming transistors in said substrate.

3. The method of claim 1 further comprising the step of coating said second metal layer with photoresist, depositing additional metal layers, patterning said additional metal layers to form hinges, beams, and posts, and removing said photoresist.

4. The method of claim 1, further comprising the step of:

patterning said blocking layer to form at least two regions, a first region in electrical contact with said electrically active regions, and a second region not in electrical contact with said electrically active regions.

5. The method of claim 1, further comprising the step of:

patterning said blocking layer to form at least two regions, a first region in electrical contact with said address electrode, and a second region in electrical contact with said landing electrode.

6. The method of claim 1, further comprising the step of:

depositing an oxide layer on said substrate prior to depositing said blocking layer.

7. The method of claim 1, further comprising the step of:

depositing an oxide layer on said blocking layer prior to depositing said electrode layer.