Method for making termination structure for power MOSFET

• US 5,597,765 A
• Filed: 04/17/1995
• Issued: 01/28/1997
• Est. Priority Date: 01/10/1995
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Yilmaz, Hamza
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/423,588
• Time in Patent Office: 652 Days
• Field of Search: 437/41, 437/42, 437/40, 437/203, 437/49, 437/52
• US Class Current: 438/270
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A termination structure (located along a transistor perimeter or a die edge) for a trenched MOSFET or other semiconductor device prevents the undesirable surface channelling phenomena without the need for any additional masking steps to form a channel stop. This structure is especially applicable to P-channel MOSFETs. In the prior art a mask defines a doped channel stop. Instead here, a blanket ion implantation of P-type ions is performed after the active area masking process. Thus this doped channel stop termination is in effect masked during fabrication by the field oxide. In another version the channel stop termination is an additional trench formed in the termination region of the MOSFET. The trench is conventionally lined with oxide and filled with a conductive polysilicon field plate which extends to the edge of the die. In another version, the doped and trenched channel stops are used in combination. The channel stops are enhanced by provision of field plates overlying them on the die surface.

Claims

1. A method of forming a trenched semiconductor transistor device including a channel stop, comprising the steps of:

providing a substrate having a principal surface and being doped with a dopant of a first conductivity type;

forming a field oxide layer on portions of the principal surface, the field oxide layer not being present on a portion of the principal surface towards an edge of the substrate which is a termination region of the transistor;

implanting a dopant of the first conductivity type into the entire principal surface, thereby forming a doped channel stop region in the termination region;

implanting a dopant of a second opposite conductivity type in a central portion of the substrate, thereby forming a body region of the transistor;

forming a trench in the central portion of the substrate; and

forming a conductive gate electrode in the trench.

2. The method of claim 1, further comprising the step of forming a conductive layer overlying the principal surface at the doped channel stop region and extending to an edge of the substrate.

3. The method of claim 1, wherein the field oxide layer overlies a portion of the principal surface between the body region and the doped channel stop region and does not extend over the doped channel stop region.

4. The method of claim 1, wherein the step of forming the field oxide layer includes locally oxidizing portions of the principal surface of the substrate.

5. The method of claim 1, wherein the step of forming the field oxide layer includes:

growing a layer of field oxide over the principal surfaces of the substrate; and

patterning the layer of field oxide.

6. The method of claim 1, further comprising the steps of:

forming a trench in the termination region; and

filling the trench with a conductive structure.

7. A method of forming a trenched semiconductor device including a channel stop in a substrate of a first conductivity type, comprising the steps of:

forming at least one active transistor body region in a central part of the substrate and doped with a dopant of a second opposite conductivity type;

forming at least two trenches in the substrate, a first trench being formed in the central part of the substrate and a second trench towards an edge of the substrate;

insulating interior walls of the trenches; and

forming conductive structures in the first and second trenches and extending over a principal surface of the substrate, wherein a portion of the substrate doped the first conductivity type is immediately laterally adjacent the second trench, whereby the second trench is a channel stop termination structure.

8. The method of claim 7, further comprising the step of forming a field oxide layer on the principal surface between the first and second trenches.

9. The method of claim 7, wherein the step of forming conductive structures includes the steps of:

filling the first and second trenches with polycrystalline silicon; and

doping the polycrystalline silicon.

10. The method of claim 7, wherein the second trench extends to an edge of the substrate.

11. The method of claim 8, wherein the conductive structure in the second trench extends from a lateral edge of the field oxide layer to an edge of the substrate.