Peak voltage and peak slope detector for a battery charger circuit

• US 5,598,086 A
• Filed: 08/03/1995
• Issued: 01/28/1997
• Est. Priority Date: 08/03/1995
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Somerville, Thomas A.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): TOATLEY, GREGORY J
• Application Number:
  US08/510,999
• Time in Patent Office: 544 Days
• Field of Search: 320/22, 320/32, 320/33, 320/39, 324/433, 324/436, 340/635, 340/636
• US Class Current: 320/148
• CPC Class Codes: H02J 7/007184 in response to battery voltage gradient

Abstract

A peak voltage and peak slope detector circuit (41) of high resolution is disclosed for sensing a battery voltage during a battery charging sequence. Battery charging circuitry is disabled when a battery voltage is being sampled to eliminate error due to noise. The battery voltage is sampled at predetermined intervals for a predetermined time period which is determined by a sample timer (46). A Voltage To Frequency Converter (42) converts the battery voltage to a signal. The signal frequency corresponds to the magnitude of the battery voltage. The number of pulses output by the VFC (42) are counted during the predetermined time period. The number of pulses are counted and compared against a previous sample by a counter comparator (44) to determine peak voltage. The peak voltage occurs when the sampled count is less than the previous sample count. The rate of change of the battery voltage is monitored by a second counter comparator (47) for determining peak slope during the battery charging sequence.

Claims

1. A peak voltage and peak slope detector circuit for a battery charger circuit comprising:

a Voltage to Frequency Converter (VFC) responsive to a battery voltage for providing a VFC signal;

a first counter comparator responsive to said VFC for generating a pulse count of said VFC signal during a predetermined time period wherein said pulse count corresponds to a voltage magnitude of said battery voltage and wherein said pulse count is compared against a previous pulse count to determine when a peak voltage occurs; and

a timer circuit for gating said VFC signal to said first counter comparator for said predetermined time period.

2. The peak voltage and peak slope detector circuit as recited in claim 1 wherein said VFC is a synchronous VFC and is responsive to a clock signal provided by said timer circuit.

3. The peak voltage and peak slope detector circuit as recited in claim 1 wherein said first comparator comprises:

an up counter for counting pulses of said VFC signal;

a down counter; and

a load logic circuit for coupling said up counter to said down counter.

4. The peak voltage and peak slope detector circuit as recited in claim 3 wherein prior to a battery voltage sample sequence said load logic circuit couples a pulse count of said up counter to said down counter for being stored therein, said pulse count of said up counter corresponding to said previous pulse count.

5. The peak voltage and peak slope detector circuit as recited in claim 4 wherein said down counter is responsive to said VFC signal during said battery voltage sample sequence, said down counter being decremented by said VFC signal during said predetermined time period.

6. The peak voltage and peak slope detector circuit as recited in claim 5 wherein said battery voltage is equal to a previous sampled battery voltage when said down counter decrements to a zero count.

7. The peak voltage and peak slope detector circuit as recited in claim 6 wherein said battery voltage is greater than a previous sampled battery voltage when said down counter decrements below a zero count and wherein a Carry signal is generated when said battery voltage is greater than said previous sampled battery voltage.

8. The peak voltage and peak slope detector as recited in claim 7 wherein said battery voltage is less than said previous sampled battery voltage when said down counter decrements above a zero count and wherein a peak voltage signal is provided for stopping a battery charging process.

9. The peak voltage and peak slope detector as recited in claim 8 wherein said zero count of said down counter enables said up counter for counting any other pulses from said VFC during said predetermined time period.

10. The peak voltage and peak slope detector as recited in claim 9 further including a second counter comparator for counting said Carry signals over a predetermined number of battery voltage sample sequences.

11. The peak voltage and peak slope detector as recited in claim 10 wherein said second counter comparator compares said pulse count corresponding to said rate of voltage change against a previous pulse count corresponding to a previous rate of voltage change and wherein a peak slope signal is provided indicating a peak slope has occurred when said pulse count is less than a previous pulse count of said second counter comparator.

12. A peak voltage and peak slope detector circuit for a battery charger circuit comprising:

a Voltage To Frequency Converter (VFC) having a first input coupled to a battery being charged and an output;

a logic circuit having a first input coupled to said output of said VFC, a second input, and an output;

a first counter comparator having a first input coupled to said output of said logic circuit, a second input, a Peak Voltage output, an Overvoltage output, and a Carry output; and

a timer circuit having a first output coupled to said second input of said logic circuit, a second output coupled to said second input of said counter comparator, and a Power Down output for turning off the battery charger circuit prior to a battery voltage sampling sequence wherein said timer circuit provides a signal to said logic circuit for gating a VFC signal for a predetermined time period to said first counter comparator and wherein said first counter comparator generates a pulse count of said VFC signal during said predetermined time period, said pulse count corresponds to a voltage magnitude of said battery, said first counter comparator comparing said pulse count against a previous pulse count for determining when a voltage peak occurs.

13. The peak voltage and peak slope detector circuit of claim 12 wherein said logic circuit comprises an AND gate having a first input coupled to said output of said VFC, a second input coupled to said first output of said timer circuit, and an output coupled to said first input of said first counter comparator.

14. The peak voltage and peak slope detector circuit as recited in claim 12 wherein said first counter comparator comprises:

an up counter for counting pulses of said VFC signal;

a down counter; and

a load logic circuit for coupling said up counter to said down counter.

15. The peak voltage and peak slope detector circuit as recited in claim 14 wherein prior to said battery voltage sample sequence said load logic circuit couples a pulse count of said up counter to said down counter for being stored therein, said pulse count of said up counter corresponding to said previous pulse count and wherein said down counter is responsive to said VFC signal during said battery voltage sample sequence, said down counter being decremented by said VFC signal during said predetermined time period.

16. The peak voltage and peak slope detector circuit as recited in claim 15 wherein said battery voltage is equal to a previous sampled battery voltage when said down counter decrements to a zero count, wherein said battery voltage is greater than said previous sampled battery voltage when said down counter decrements below a zero count, wherein a Carry signal is generated upon receiving an additional pulse after said zero count indicating said battery voltage has increased, wherein said Carry signal enables said up counter for being incremented by any additional pulses from said VFC during said predetermined time period, and wherein said battery voltage is less than said previous sampled battery voltage when said down counter decrements above a zero count, the peak voltage and peak slope detector circuit indicating a peak voltage has occurred at said Peak Voltage output after said predetermined time period.

17. The peak voltage and peak slope detector circuit as recited in claim 16 further including a second counter comparator coupled for receiving said Carry signal, said second counter comparator detecting peak slope by comparing a count of said Carry signals for a predetermined number of battery voltage sample sequences against a previous count of Carry signals wherein a peak slope is detected when said count of Carry signals is less than a previous count of Carry signals.

18. A method for detecting peak voltage and peak slope of a battery being charged, the method comprising the steps of:

converting a battery voltage to a signal wherein a pulse count of said signal over a predetermined time period corresponds to a magnitude of said battery voltage;

generating a pulse count of said signal during said predetermined time period;

decrementing a previous pulse count corresponding to a previous sampled battery voltage with said signal wherein a peak voltage is detected when said previous pulse count does not reach a zero count; and

providing a Carry signal indicating said battery voltage is greater than said previous sampled battery voltage when said previous pulse count is decremented below said zero count.

19. The method as recited in claim 18 further including the steps of:

generating a count of Carry signals for a predetermined number of sampled battery voltages wherein a count of said Carry signals indicates a rate of change of said battery voltage;

comparing a previous count of Carry signals against said count wherein peak slope occurs when said count of said Carry signals is less than said previous count of said Carry signals.