Switchable current source for digital-to-analog converter (DAC)

• US 5,598,095 A
• Filed: 03/08/1995
• Issued: 01/28/1997
• Est. Priority Date: 03/08/1995
• Status: Expired due to Term

• Current Assignee: Shared Memory Graphics LLC (Acacia Research Corporation)
• Original Assignee: Alliance Semiconductor Corporation
• Inventors: Schnaitter, William N.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): BERHANE, ADOLF D
• Application Number:
  US08/401,022
• Time in Patent Office: 692 Days
• Field of Search: 323/312, 323/315, 323/317, 327/530, 327/538, 341/144
• US Class Current: 323/315
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A switchable current source (10) for video DACs that reduces output transients. The switchable current source (10) includes a current mirror (20) connected to a cascode pair (22) for providing a reference current input and a current output. Connected to the reference current input is reference current generator (14) that includes p-channel transistor Q5 for providing a reference current according to the voltage applied at its gate by voltage source (24). A current switch (16) is connected to the current output and includes p-channel transistor Q6 for providing a path to ground and p-channel transistor Q7 for providing a path to an output node. In response to a decoder input DEC, an enable signal generator (18) outputs an enable signal EN and an inverted enable signal ENI to Q7 and Q6, respectively. The enable signal generator (18) includes a delay path (30 and 34) for both the EN and ENI signals so that during a low-to-high transition of signal DEC, EN is delayed so that ENI turns Q7 on before EN shuts off Q6. During a high-to-low transition of DEC, ENI is delayed so that Q6 is turned on before Q7 is turned off.

Claims

1. A switchable current source comprising:

a current source having a reference input and a current output;

reference current means coupled to the reference input for supplying a reference current to said current source;

signal generating means for generating an enable signal; and

current switch means coupled to the current output for switching the current output path between an output node and a ground node, said current switch means responsive to the enable signal such that a first current path is provided between the current output and the output node prior to disabling a second current path between the current output and the ground node.

2. The switchable current source of claim 1 wherein:

said signal generating means generates a disable signal; and

said current switch means is responsive to the disable signal such that the second current path is provided between the current output and the ground node prior to disabling the first current path between the current output and the output node.

3. The switchable current source of claim 1 wherein:

said current source includes a current mirror having a first MOS reference transistor and a first MOS source transistor, the current mirror being coupled to a cascode pair of MOS transistors, the cascode pair having a second MOS reference transistor and a second MOS source transistor.

4. The switchable current source of claim 3 wherein:

said current source is comprised of PMOS transistors.

5. The switchable current source of claim 1 wherein:

said reference current means is a biased MOS reference transistor.

6. The switchable current source of claim 5 wherein:

the MOS reference transistor is a PMOS transistor connected by its source to the reference input of said current source, by its drain to a ground node, and by its gate to a reference bias voltage.

7. The switchable current source of claim 1 wherein:

said current switch means includes at least one MOS current switch.

8. The switchable current source of claim 7 wherein:

said signal generating means is responsive to a decode input signal, and the enable signal includes a switch signal and a complementary switch signal; and

said current switch means includes a first MOS switch transistor coupled between the current output and the ground node, and a second MOS switch transistor coupled between the current output and the output node, the gate of the first MOS switch transistor receiving the switch signal, and the gate of the second MOS switch transistor receiving the complementary switch signal.

9. The switchable current source of claim 8 wherein:

said signal generating means further includes

a first delay means responsive to a first logic transition in the decode input signal for delaying the enable signal; and

a second delay means responsive to a second logic transition in the decode input for delaying the complementary enable signal.

10. The switchable current source of claim 8 wherein:

the first MOS switch transistor is a PMOS transistor and the second MOS switch transistor is a PMOS transistor.

11. In a current scaling digital-to-analog converter, a current source and switching circuit for providing an output current, comprising:

at least one current source having a first transistor and a second transistor, the first transistor being gate coupled to both its drain and to the gate of the second transistor, said current source providing a current input transistor and a current output transistor;

bias means coupled to the drain of the current input transistor for providing a reference current;

enable signal means responsive to an enable input for generating a first enable signal and a second enable signal, said enable signal means including a first delay means for delaying the first enable signal;

a first current switch coupled to the drain of the current output transistor, said first current switch responsive to the first enable signal; and

a second current switch coupled to the drain of the current output transistor, said second current switch responsive to the second enable signal.

12. The current source and switching circuit of claim 11 wherein:

the transistors of said plurality of current sources are p-channel MOS devices.

13. The current source and switching circuit of claim 12 wherein:

said current source further includes a third transistor and a fourth transistor, the third transistor being coupled by its source to the drain of the first transistor, the fourth transistor being coupled by its source to the drain of the second transistor, the third transistor being the current input transistor, the fourth transistor being the current output transistor.

14. The current source and switching circuit of claim 12 wherein:

said bias means includes

a bias voltage source for providing a bias voltage; and

a p-channel MOS device having its source coupled to the drain of the current input transistor and its gate coupled the bias voltage source.

15. The current source and switching circuit of claim 12 wherein:

said first current switch is a p-channel MOS device having its gate coupled to the first enable signal, its drain coupled to the source of the current output transistor, and its source coupled to ground.

16. The current source and switching circuit of claim 12 wherein:

said second current switch is a p-channel MOS device having its gate coupled to the second enable signal, its drain coupled to the source of the current output transistor, and its source coupled to an output node.

17. The current source and switching circuit of claim 11 wherein:

the enable input to said enable means changes between at least a first logic transition and a second logic transition; and

said enable signal means further includes

a first signal branch including the first delay means, the first delay means responsive to the first logic transition for delaying the first enable signal, and

a second signal branch including a second delay means, the second delay means responsive the second logic transition for delaying the second enable signal.

18. The current source and switching circuit of claim 17 wherein:

the first signal branch includes a first delay path, a first direct path, and a first logic gate, the first delay path and the first direct path receiving the enable input and providing inputs to the first logic gate; and

the second signal branch includes an input inverter, a second direct path, a second delay path and a second logic gate, the input inverter receiving the enable input and providing an output to the second direct path and the second delay path which provide inputs to the second logic gate.

19. The current source of claim 18 wherein:

the first delay path and second delay path of the enable signal means each include a plurality of delay inverters.

20. The current source of claim 18 wherein:

the first logic gate and the second logic gate of the enable signal means each include a NAND gate and an output inverter, each NAND gate receiving the inputs from its respective delay and direct paths and providing an input to its respective output inverter, the output inverters providing the first enable signal and the second enable signal.